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Abstract: The high clock frequencies of modern superscalar processors make the wire delay incurred in moving data across the processor chip a significant concern. As frequencies continue to increase, it will become more di#cult for a centralized first level data cache to supply the timely data bandwidth required by superscalar processors. (Update)
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BibTeX entry: (Update)
@misc{ racunas-partitioned,
author = "Microarchitectures Paul Racunas",
title = "Partitioned First-Level Cache Design for Clustered",
url = "citeseer.ist.psu.edu/664656.html" }
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62 The multicluster architecture: Reducing cycle time through p.. - Farkas, Chow et al. - 1997
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12 Two fast and high-associativity cache schemes - Zhang, Zhang et al. - 1997
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7 Access region locality for high-bandwidth processor memory s.. - Cho, Yew et al. - 1999
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5 Two-ported cache alternatives for superscalar processors (context) - Wolfe, Boleyn - 1993
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1 Parallel cachelets (context) - Limaye, Rakvic et al. - 2001
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