William F. Richardson, Erik Brunvand  Home/Search
Context Related
| utah.edu/techreports/...UUCS95008.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: utah.edu/techreports/ (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Decoupled computer architectures provide aneff. (Update)
Context of citations to this paper: More
...design, such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [9,10,11]. A prototype of Fred has been implemented as a detailed VHDL model to investigate the performance 2 and behavior of the Fred...
...such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [33,34]. Detailed descriptions of the most recent implementation are contained in the following chapters. 1 Fred is not an acronym, and it...
Cited by: More
High-Frequency Pipeline Architecture Using the.. - Gschwind, Kosonocky.. (2001) (Correct)
Decoupled Pipelines: Rationale, Analysis, and Evaluation - Frederick Koopmans Sanjay (Correct)
Architectural Considerations in Silf-Timed Processor Design - Richardson (1996) (Correct)
Similar documents (at the sentence level):
59.9%: Fred: An Architecture for a Self-Timed Decoupled Computer - Richardson, Brunvand (1996) (Correct)
5.9%: Precise Exception Handling for a Self-Timed Processor - Richardson, Brunvand (1995) (Correct)
5.9%: Architectural Considerations for a Self-Timed Decoupled.. - Richardson, Brunvand (Correct)
Active bibliography (related documents): More All
0.5: Dynamic Resource Management in a Cluster for.. - Gallard, Morin, Lottiaux (Correct)
0.3: Loop Optimization Techniques On Multi-Issue Architectures - Kaiser (Correct)
0.3: Multithreading Decoupled Architectures for.. - Sung, Krashinsky.. (2001) (Correct)
Similar documents based on text: More All
0.7: The NSR Processor Prototype - Richardson, Brunvand (1992) (Correct)
0.3: A Correctness Criterion for Asynchronous Circuit.. - Gopalakrishnan.. (1992) (Correct)
0.1: Impulse: Building a Smarter Memory Controller - Carter, Hsieh, Stoller.. (1999) (Correct)
Related documents from co-citation: More All
4: Asynchronous advantages often cited and NOT often cited (context) - Davis - 1994
4: An Out-of-Order Superscalar Processor with Speculative Execution and Fast (context) - Dwyer, Torng - 1992
3: Precise exception handling for a self-timed processor - Richardson, Brunvand - 1995
BibTeX entry: (Update)
W. F. Richardson, E. L. Brunvand, FRED : An Architecture for a Self-Timed Decoupled Computer », Computer Science Department, University of Utah, 1997. http://citeseer.ist.psu.edu/article/richardson95fred.html More
@techreport{ richardson95fred,
author = "William F. Richardson and Erik Brunvand",
title = "Fred: An Architecture for a Self-Timed Decoupled Computer",
number = "UUCS-95-008",
month = "8,",
year = "1995",
url = "citeseer.ist.psu.edu/article/richardson95fred.html" }
Citations (may not include all citations):230 Limits of instruction-level parallelism - Wall - 1990
83 Communications of the ACM (context) - Sutherland - 1989
80 The design of an asynchronous microprocessor (context) - Martin, Burns et al. - 1989
67 Measuring the parallelism available for very long instructio.. (context) - Nicolau, Fisher - 1984
65 PIPE: A VLSI decoupled architecture (context) - Goodman, Hsieh et al. - 1985
43 A micropipelined ARM - Furber, Day et al. - 1993
37 Counterflow pipeline processor architecture - Sproull, Sutherland - 1994
28 Reduced Instruction Set Computer Architectures for VLSI (context) - Katevenis - 1985
28 The Design and Implementation of an Asynchronous Microproces.. (context) - Paver - 1994
17 The NSR processor (context) - Brunvand - 1993
9 Interrupt handling for out-of-order execution processors (context) - Torng, Day - 1993
7 The WM computer architecture (context) - Wulf - 1988
5 Using FPGAs to prototype a self-timed computer (context) - Brunvand - 1992
5 The NSR processor prototype - Richardson, Brunvand - 1992
4 The architecture and system method for DDM1: A recursively s.. (context) - Davis - 1978
4 Macromodular system design (context) - Clark, Molnar - 1973
4 Precise exception handling for a self-timed processor - Richardson, Brunvand - 1995
3 A comparison of superscalar and decoupled access /execute ar.. - Farrens, Ng et al. - 1993
3 Hardware /software tradeoffs for increased performance (context) - Hennessy, Jouppi et al. - 1982
2 ACM Transactions on Computer Systems (context) - Gross, Hennessy et al. - 1988
1 MCola RISC Microprocessor User's Manual (context) - ola, User et al. - 1990
Documents on the same site (http://www.cs.utah.edu/techreports/): More
Instrumented Sensor System - Practice - Dekhil, Henderson (1997) (Correct)
Notes on Thread Models in Mach3.0 - Ford, Hibler, Lepreau (1993) (Correct)
A Fast Parallel Squarer Based on Divide-and-Conquer - Yoo, Smith, Gopalakrishnan (1995) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC