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Abstract: This work is focused on accelerating upgrade misses in cc-NUMA multiprocessors. These misses are caused by store instructions for which a read-only copy of the line is found in the L2 cache. Upgrade misses require a message sent from the missing node to the directory, a directory lookup in order to find the set of sharers, invalidation messages being sent to the sharers and responses to the invalidations being sent back. Therefore, the penalty paid by these misses is not negligible, mainly if... (Update)
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BibTeX entry: (Update)
@misc{ acacio-use,
author = "Multiprocessors Manuel Acacio",
title = "The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA",
url = "citeseer.ist.psu.edu/649512.html" }
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2 A Novel Approach to Reduce L2 Miss Latency in SharedMemory M.. (context) - Acacio, Gonzalez et al. - 2002
1 A Novel Multicast Scheme to Reduce Cache Invalidation Overhe.. - Zhou, Shi et al. - 2000
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