Rajesh Nishtala, Richard W. Vuduc, James W. Demmel, Katherine A. Yelick  Home/Search
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Abstract: SpMV), or y = y +A x, which is an important and ubiquitous computational kernel. Prior work indicates that cache blocking of SpMV is extremely important for some matrix and machine combinations, with speedups as high as 3x. In this paper we present a new, more compact data structure for cache blocking for SpMV and look at the general question of when and why performance improves. Cache blocking appears to be most e#ective when simultaneously 1) the vector x does not fit in cache 2) the... (Update)
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BibTeX entry: (Update)
R. Nishtala, R. W. Vuduc, J. W. Demmel, and K. A. Yelick. Performance modeling and analysis of cache blocking in sparse matrix vector multiply. Technical report, University of California, Berkeley, EECS Dept., 2004. (to appear). http://citeseer.ist.psu.edu/article/nishtala04performance.html More
@misc{ nishtala04performance,
author = "R. Nishtala and R. Vuduc and J. Demmel and K. Yelick",
title = "Performance modeling and analysis of cache blocking in sparse matrix vector
multiply",
text = "R. Nishtala, R. W. Vuduc, J. W. Demmel, and K. A. Yelick. Performance modeling
and analysis of cache blocking in sparse matrix vector multiply. Technical
report, University of California, Berkeley, EECS Dept., 2004. (to appear).",
year = "2004",
url = "citeseer.ist.psu.edu/article/nishtala04performance.html" }
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