Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai  Home/Search
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Abstract: An increasing cache latency in future processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. In this paper, we describe an early address resolution mechanism that accurately resolves both regular and irregular load addresses. The basic idea is to build dynamic dependence links from the instruction that updates the base register to the consumer load instructions. Once a new base address is available, it triggers calculations of the new load... (Update)
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BibTeX entry: (Update)
@misc{ chung-direct,
author = "Byung-Kwon Chung and Jinsuo Zhang and Jih-Kwon Peir and Shih-Chang Lai
and Konrad Lai",
title = "Direct Load: Dependence-Linked Dataflow Resolution of Load Address and
Cache Coordinate",
url = "citeseer.ist.psu.edu/627493.html" }
Citations (may not include all citations):190 Value Locality and Load Value Prediction - Lipasti, Wilkerson et al. - 1996
161 The SimpleScalar Tool Set (context) - Burger, Austin - 1997
132 The Alpha 21264 Microprocessor (context) - Kessler - 1999
116 Highly Accurate Data Values Prediction using Hybrid Predicto.. - Wang, Franklin - 1997
73 Dependence Based Prefetching for Linked Data Structures - Roth, Moshovos et al. - 1998
64 Memory Dependence Prediction using Store Sets - Chrysos, Emer - 1998
57 A Load-Instruction Unit For Pipelined Processors (context) - Eickemeyer, Vassiliadis - 1993
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36 Tuning the Pentium Pro Microarchitecture (context) - Papworth - 1996
29 Next Cache Line and Set Prediction - Calder, Grunwald - 1995
28 Correlated Load-Address Predictors - Bekerman, Jourdan et al. - 1999
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21 UltraSPARC-III: Designing Third-Generation 64-Bit Performanc.. (context) - Horel, Lauterbach - 1999
13 Microprocessor Design (context) - Slegel - 1999
8 Early Load Address Resolution Via Register Tracking - Bekerman, Yoaz et al. - 2000
6 Low Load Latency through Sum-Addressed Memory (context) - Lynch, Lauterbach et al. - 1998
6 CompilerDirected Early Load-Address Generation - Cheng, Connors et al. - 1998
5 Early Resolution of Address Translation in Cache Design (context) - Hua, Hunt et al. - 1990
4 History Table for Set Prediction for Accessing a Set-Associa.. (context) - Liu - 1995
3 IBM's Power to Replace PSC (context) - Power, SC et al. - 1997
3 Microarchitecture Support for Improving the Performance of L.. (context) - Chen, Wu - 1997
2 Data ow Analysis of Branch Mispredictions and Its Applicatio.. (context) - Farcy, Temam et al. - 1998
1 ith, \The Predictability of Data Values," Proc. of 30th annu.. (context) - Sazeides, Sm - 1997
1 ective Address Prediction of Load Instructions (context) - Ahuja, Emer et al. - 2001
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