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by Rolf Drechsler, Wolfgang Gunther, Thomas Eschbach, Lothar Linhard, Gerhard Angst, R. Drechsler, W. Gunther, T. Eschbach, L. Linhard, G. Angst
Euromicro Symposium on DSD
ftp://ftp.informatik.uni-freiburg.de/documents/reports/report164/report00164.ps.gz
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Abstract:
In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g. more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided in several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to the state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four. The proposed method has been integrated in a commercially available tool. 1
Citations
|
783
|
An efficient heuristic procedure for partitioning graphics, The Bell Syst
– Kemighan, Lin
- 1970
|
|
306
|
A linear-time heuristic for improving network partition
– Fiduccia, Mattheyses
- 1982
|
|
171
|
Recent Directions In Netlist Partitioning: a Survey
– Alpert, Kahng
- 1995
|
|
162
|
Multilevel hypergraph partitioning: applications in vlsi domain
– Karypis, Aggarwal, et al.
- 1999
|
|
118
|
The ISPD98 circuit benchmark suite
– Alpert
- 1998
|
|
112
|
An improved min-cut algorithm for partitioning VLSI networks
– Krishnamurthy
- 1984
|
|
107
|
Multiple-way network partitioning
– Sanchis
- 1989
|
|
79
|
Multilevel k-way hypergraph partitioning
– Karypis, Kumar
- 1999
|
|
70
|
Multilevel circuit partitioning
– Alpert, Huang, et al.
- 1997
|
|
54
|
Improving the performance of Kernighan–Lin and simulated annealing graph bisection algorithms
– Bui
- 1989
|
|
48
|
2-layer straightline crossing minimization: performance of exact and heuristic algorithms
– Jünger, Mutzel
- 1997
|
|
27
|
Partitioning of VLSI Circuits and Systems
– Johannes
- 1996
|
|
20
|
P.: Using sifting for k-layer straightline crossing minimization
– Matuszewski, Schönfeld, et al.
- 1999
|
|
18
|
New faster Kernighan–Lin-type graph-partitioning algorithms
– Dutt
- 1993
|
|
18
|
hMetis: A Hypergraph Partitioning Package
– Karypis, Kumar
- 1998
|
|
8
|
Arc crossing minimization in hierarchical digraphs with tabu search
– Laguna, Martí, et al.
- 1997
|
|
4
|
Automatic Generation of Digital System Schematics, 22nd Design Automation Conf
– Arya, Kumar, et al.
- 1985
|
|
2
|
Level assignment for displaying combinational logic
– Drechsler, Gunther, et al.
- 2001
|
|
2
|
ASG: Automatic schematic generator
– Jehng, Chen, et al.
- 1991
|
|
1
|
GREEDY IIP: Partitioning large graphs by greedy it
– Becker, Drechsler, et al.
|
|
1
|
Multiple-way partitioning with different cost functions
– Sanchis
- 1993
|
|
1
|
An evaluation of move-based multi-way partitioning algorithms
– Yarack, Carletta
- 2000
|
