Alvin R. Lebeck, Jinson Koppanalil, Tong Li, Jaidev Patwardhan, Eric Rotenberg  Home/Search
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Abstract: Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately, naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism. This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of... (Update)
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BibTeX entry: (Update)
@misc{ lebeck-large,
author = "Alvin R. Lebeck and Jinson Koppanalil and Tong Li and Jaidev Patwardhan
and Eric Rotenberg",
title = "A Large, Fast Instruction Window for Tolerating Cache Misses",
url = "citeseer.ist.psu.edu/615984.html" }
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