Delay and noise estimation of CMOS logic gates driving coupled...  Home/Search
Context
Related
| rochester.edu:8080...integration.00.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: rochester.edu/~fri...publications (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of... (Update)
Active bibliography (related documents): More All
1.8: Noise Estimation Due To Signal Activity For Capacitively.. - Tang, Friedman (2000) (Correct)
1.0: Interconnect Coupling Noise in CMOS VLSI Circuits - Tang, Friedman (1999) (Correct)
0.6: Aggressor Alignment for Worst-Case Coupling Noise - Chen, Malgorzata (2000) (Correct)
Similar documents based on text: More All
0.5: Lumped Versus Distributed RC and RLC Interconnect Impedances - Tang, Friedman (Correct)
0.3: Estimation of On-Chip Simultaneous Switching Noise in VDSM.. - Tang, Friedman (Correct)
0.3: Transient Analysis of a CMOS Inverter Driving Resistive.. - Tang, Friedman (2000) (Correct)
BibTeX entry: (Update)
@misc{ delay-integration,
author = "Delay And Noise",
title = "INTEGRATION, the VLSI journal 29 (2000) 131}165",
url = "citeseer.ist.psu.edu/613168.html" }
Citations (may not include all citations):179 and Packaging for VLSI (context) - Bakoglu, Interconnections - 1990
170 The National Technology Roadmap for Semiconductors (context) - Association - 1997
170 The National Technology Roadmap for Semiconductor (context) - Association - 1994
76 Alpha-power law MOSFET model and its application to CMOS inv.. (context) - Sakurai, Newton - 1990
33 Simple formulas for two- and three-dimensional capacitances (context) - Sakurai, Tamaru - 1983
28 Closed-form expression for interconnection delay (context) - Sakurai - 1993
20 GlobalHarmony: coupled noise analysis for full-chip RC inter.. (context) - Shepard, Narayanan et al. - 1997
17 Multilevel metal capacitance models for CAD design synthesis.. (context) - Chern - 1992
16 Calculating worst-case gate delay due to dominant capacitive.. - Dartu, Pileggi - 1997
16 A simple MOSFET model for circuit analysis (context) - Sakurai, Newton - 1991
16 Delay and noise formulas for capacitively coupled distribute.. (context) - Kawaguchi, Sakurai - 1998
13 Circuit implementation of a 300-MHz 64-bit second-generation.. (context) - Bowhill - 1995
8 VLSI Technology (context) - Sze - 1988
8 Line-to-ground capacitance calculation for VLSI: a compariso.. (context) - Barke - 1998
8 Noise and delay uncertainty studies for coupled RC interconn.. - Kahng, Muddu et al. - 1999
6 reduction and avoidance of crosstalk on VLSI chips (context) - Stohr, Alt et al. - 1998
5 Theory of CMOS Digital Circuits and Circuit Failures (context) - Shoji - 1992
3 Substrate injection and crosstalk in CMOS circuits (context) - Briaire, Krisch - 1999
3 An approach to the analysis and detection of crosstalk fault.. (context) - Rubio, Itazaki et al. - 1994
3 Latching characteristics of a CMOS bistable register (context) - Friedman - 1993
3 Interconnect capacitance models for VLSI circuits (context) - Wong - 1988
3 Interconnect coupling noise in CMOS VLSI circuits - Tang, Friedman - 1999
2 A physical alpha-power law MOSFET model (context) - Bowman, Austin et al. - 1999
2 The war on noise: new tools needed to attack the noise probl.. (context) - Patton - 1998
2 Modeling crosstalk in resistive VLSI interconnections (context) - Vittal, Chen et al. - 1999
2 chip crosstalk-the new signal integrity challenge (context) - Gal - 1995
2 Sangiovanni-Vincentelli (context) - Quarles, Newton et al. - 1988
2 Inductance and capacitance formulas for VLSI interconnects (context) - Delorme, Belleville et al. - 1996
1 ULSI Technology (context) - Chang, Sze - 1996
1 cient coupled noise estimation for on-chip interconnects (context) - Devgan - 1997
1 ects of interconnections on high-speed logic circuits (context) - Jarvis - 1963
1 A methodology for estimating interconnect capacitance for si.. (context) - Gilligan, Gupta - 1995
1 and signal delay (context) - Cho, Eo et al. - 1996
1 A fringing and coupling interconnect line capacitance model .. (context) - Lee - 1996
1 Planning for signal integrity (context) - Johnson - 1997
1 Aided Design Integrated Circuits Systems CAD (context) - Hedenstierna, Jeppson et al. - 1987
1 Signal integrity: tools issue (context) - Shah - 1997
1 Solid State Technol (context) - Lee, interconnects-gigahertz - 1998
1 Noise estimation due to signal activity for capacitively cou.. - Tang, Friedman - 2000
Documents on the same site (http://www.ece.rochester.edu/~friedman/publications.html): More
Optimal Clock Skew Scheduling Tolerant to Process Variations - Neves, Friedman (1996) (Correct)
Demonstration Of Speed Enhancements On An.. - Velenis, Tang.. (Correct)
Large Scale Clock Skew Scheduling Techniques For Improved - Reliability Of Digital (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC