in the VIRAM Compiler David Judd, Katherine Yelick, Christoforos Kozyrakis,...  Home/Search
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Abstract: Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of the VIRAM architecture from the perspective of compiler writers, describing some of the code generation problems that arise in VIRAM and their solutions in the VIRAM compiler. VIRAM is a single chip system designed primarily for multi-media. It combines vector processing with mixed logic and DRAM to acheive high ... (Update)
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BibTeX entry: (Update)
@misc{ viram-exploiting,
author = "In The Viram",
title = "Exploiting On-Chip Memory Bandwidth",
url = "citeseer.ist.psu.edu/600625.html" }
Citations (may not include all citations):135 MMX technology extension to the intel architecture (context) - Peleg, Weiser - 1996
44 Bitwidth analysis with application to silicon compilation - Stephenson, Babb et al. - 2000
31 A case for Intelligent DRAM: IRAM (context) - Patterson, Anderson et al. - 1997
22 Simple vector microprocessors for multimedia applications - Lee, Stoodley - 1998
7 A second generation SIMD microprocessor architecture (context) - Phillip - 1998
7 A media-enhanced vector architecture for embedded memory sys.. - Kozyrakis - 1999
4 An architectural performance study of the fast fourier trans.. - Thomas - 2000
2 ciency of IRAM architectures (context) - Fromm, Perissakis et al. - 1997
1 LAPACK Users' Guide: Third Edition (context) - Anderson, Bai et al. - 1999
Documents on the same site (http://iram.cs.berkeley.edu/publications.html): More
The Energy Efficiency of IRAM Architectures - Fromm, Perissakis, Cardwell.. (1996) (Correct)
Evaluation of Existing Architectures in IRAM Systems - Bowman, Cardwell.. (1997) (Correct)
Intelligent RAM (IRAM): the Industrial Setting.. - Patterson.. (Correct)
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