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Abstract: A DMA controller that operates in the cycle-stealing mode is allowed to transfer data only when the CPU does not need the system bus. Thus, the execution time of a cycle-stealing DMA I/O task depends on the sequence of instructions executing concurrently with it. This paper describes a method for bounding the worst-case execution time (WCET) of a cycle-stealing DMA I/O task. We first define the task model. We next describe several properties of instruction sequences that can execute... (Update)
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BibTeX entry: (Update)
@misc{ huang-worstcase,
author = "Tai-Yi Huang and Jane W.-S. Liu",
title = "Worst-Case Timing Analysis of Cycle-Stealing DMA I/O Tasks",
url = "citeseer.ist.psu.edu/59920.html" }
Citations (may not include all citations):1582 Scheduling algorithms for multiprogramming in a hard real-ti.. - Liu, Layland - 1973
528 Priority inheritance protocols: An approach to real-time syn.. (context) - Sha, Rajkumar et al. - 1990
336 The rate monotonic scheduling algorithm: Exact characterizat.. (context) - Lehoczky, Sha et al. - 1989
58 PERTS: A prototyping environment for real-time systems - Liu, Redondo et al. - 1993
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