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Abstract: g for network hierarchy were applied. Simulated the gate-level timing properties of digital logic circuits for the whole microprocessor chip, PERL language, HSpice TM, and Cadence TM Schematic tool were used. Wrote 10,000 around lines of codes with PERL under IRIX TM environment, to generate timing models using Object-Oriented Programming skills and to provide HSpice TM simulation input decks. Made three presentations to the department and received two awards from the company intern... (Update)
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@misc{ -unknown,
title = "Unknown",
url = "citeseer.ist.psu.edu/598801.html" }
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Documents on the same site (http://home.cwru.edu/~qxq2/):
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