Ramzi Ben Salah, Marius Bozga, Oded Maler  Home/Search
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Abstract: In this paper we report some progress in applying timed automata technology to large-scale problems. We focus on the problem of finding maximal stabilization time for combinational circuits whose inputs change only once and hence they can be modeled using acyclic timed automata. We develop a "divideand -conquer" methodology based on decomposing the circuit into sub-circuits and using timed automata analysis tools to build conservative low-complexity approximations of the sub-circuits to... (Update)
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BibTeX entry: (Update)
@misc{ salah-timing,
author = "Ramzi Ben Salah and Marius Bozga and Oded Maler",
title = "On Timing Analysis of Combinational Circuits",
url = "citeseer.ist.psu.edu/594869.html" }
Citations (may not include all citations):666 Theoretical Computer Science (context) - Alur, Dill et al. - 1994
404 Symbolic Model-checking for Real-time Systems - Henzinger, Nicollin et al. - 1994
141 Timing Assumptions and Verification of Finite-State Concurre.. (context) - Dill - 1989
98 Kronos: A verification tool for real-time systems (context) - Yovine - 1997
82 Kronos: a Model-Checking Tool for Real-Time Systems - Bozga, Daws et al. - 1998
73 Timed Automata - Alur - 1999
47 Timing Verification by Successive Approximation - Alur, Itai et al. - 1995
44 Some Progress in the Symbolic Verification of Timed Automata - Bozga, Maler et al. - 1997
38 Safety for Branching Time Semantics - Bouajjani, Fernandez et al. - 1991
37 Asynchronous Circuits (context) - Brzozowski, Seger - 1994
33 Software Tools for Technology Transfer (context) - Larsen, Pettersson et al. - 1997
31 Approximate Reachability Analysis of Timed Automata (context) - Balarin - 1996
28 Timing Analysis of Asynchronous Circuits using Timed Automat.. - Maler, Pnueli - 1995
26 Finite-state Analysis of Asynchronous Circuits with Bounded .. (context) - Lewis - 1989
21 Hardware Timing Verification using KRONOS - Maler, Yovine - 1996
18 Verifying Abstractions of Timed Systems - Tasiran, Alur et al. - 1996
16 Formal Verification of Safety Properties in Timed Circuits - Pena, Cortadella et al. - 2000
12 Protocol Verification with the Aldebaran Toolset (context) - Bozga, Fernandez et al. - 1997
11 STARI: A Case Study in Compositional and Hierarchical Timing.. - Tasiran, Brayton - 1997
7 Approximations for Verifying Timing Properties (context) - Wong-Toi, Dill - 1994
7 Efficient Verification of Timed Automata using Dense and Dis.. - Bozga, Maler et al. - 1999
5 Verification of Asynchronous Circuits using Timed Automata (context) - Bozga, Jianmin et al. - 2002
4 Computing Delay with Coupling using Timed Automata - Tasiran, Kukimoto et al. - 1997
2 A Timed Automaton-Based Method for Accurate Computation of C.. - Tasiran, Khatri et al. - 1998
1 Modular Verification of Timed Circuits using Automatic Abstr.. (context) - Zheng, Mercer et al. - 2003
1 AValidation Environment for ComponentBased Real-Time Systems (context) - Bozga, Graf et al. - 2002
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