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Abstract: We describe the architecture for a single-chip AEGIS processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all components external to the processor, such as memory, are untrusted. We show two different implementations. In the first case, the core functionality of the operating system is trusted and implemented in a security kernel. We also describe a variant implementation assuming an untrusted operating system. (Update)
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BibTeX entry: (Update)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas Devadas. aegis: Architecture for tamper-evident and tamper-resistant processing. In Proceedings of the 17 Int'l Conference on Supercomputing, June 2003. 20 http://citeseer.ist.psu.edu/article/suh03aegis.html More
@misc{ suh03aegis,
author = "G. Suh and D. Clarke and B. Gassend and M. van Dijk and S. Devadas",
title = "aegis: Architecture for tamper-evident and tamper-resistant processing",
text = "G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas
Devadas. aegis: Architecture for tamper-evident and tamper-resistant processing.
In Proceedings of the 17 Int'l Conference on Supercomputing, June 2003.
20",
year = "2003",
url = "citeseer.ist.psu.edu/article/suh03aegis.html" }
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