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Abstract: Formal techniques offer an opportunity to significantly reduce the cost of microprocessor verification. We propose a model checking based approach to automatically generate functional test programs for pipelined processors. We specify the processor architecture in an Architecture Description Language (ADL). The processor model is extracted from the ADL specification. Specific properties are applied to the processor model using SMV model checker to generate test programs. We applied this... (Update)
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BibTeX entry: (Update)
@misc{ mishra-architecture,
author = "Prabhat Mishra and Nikil Dutt",
title = "Architecture Description Language driven Functional Test Program Generation
for Microprocessors using SMV",
url = "citeseer.ist.psu.edu/571233.html" }
Citations (may not include all citations):1575 Computer Architecture: A quantitative approach (context) - Hennessy, Patterson - 1990 ACM
100 Automatic verification of pipelined microprocessor control - Burch, Dill - 1994 ACM DBLP
65 EXPRESSION: A language for architecture exploration through .. - Halambi - 1999
47 Formal verification of a pipelined microprocessor (context) - Srivas - 1990 ACM DBLP
34 Using Model Checking to Generate Tests from Specifications - Ammann - 1998 ACM DBLP
34 Test Program Generation for Functional Verification of Power.. - Aharon - 1995
33 Microprocessor verification in pvs: A methodology and simple.. - Cyrluk - 1993
21 Trace table based approach for pipelined microprocessor veri.. - Sawada - 1997
19 Test Generation for Microprocessors (context) - Thatte - 1980
17 Formal verification of superscalar microprocessors with mult.. - Velev - 2000
15 Instruction Randomization Self Test for Processor Cores (context) - Batcher - 1999 ACM
12 SAT: A visual specification and analysis tool for system-on-.. (context) - Khare - 1999
10 DEFUSE: A Deterministic Functional Self-Test Methodology for.. - Chen - 2000
10 Functional Abstraction driven Design Space Exploration of He.. - Mishra - 2001 ACM DBLP
7 Formal verification of pipeline control using controlled tok.. (context) - Ho - 1998 ACM DBLP
7 Micro architecture coverage directed generation of test prog.. (context) - Ur - 1999 ACM DBLP
6 Formal verification of out-of-order execution using incremen.. - Skakkebaek - 1998 ACM DBLP
5 Automatic Modeling and Validation of Pipeline Specifications.. - Mishra - 2002 ACM DBLP
5 the Test of Microprocessor IP Cores - Corno - 2001
4 Modeling and Verification of Pipelined Embedded Processors i.. (context) - Mishra - 2002 ACM DBLP
3 Automatic Verification of In-Order Execution in Microprocess.. (context) - Mishra - 2002 ACM DBLP
3 Automatic test pattern generation for pipelined processors (context) - Iwashita - 1994
2 Functional Verification of the Equator MAP1000 Microprocesso.. - Shen - 1999 ACM DBLP
2 Microprocessor design verification using reverse engineering (context) - Hauke, Hayes - 1999
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