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WaveScalar (2003)  (Make Corrections)  
Steven Swanson, Ken Michelson, Mark Oskin



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Abstract: Silicon technology will continue to provide an exponential increase in the availability of raw transistors. (Update)

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BibTeX entry:   (Update)

@misc{ swanson-wavescalar,
  author = "Steven Swanson and Ken Michelson and Mark Oskin",
  title = "WaveScalar",
  url = "citeseer.ist.psu.edu/article/swanson03wavescalar.html" }
Citations (may not include all citations):
983   The Art of Scientific Computing (context) - Press, Teukolsky et al. - 1992
415   Efficiently computing static single assignment form and the .. - Cytron, Ferrante et al. - 1991
320   Mediabench: A tool for evaluating and synthesizing multimedi.. - Lee, Potkonjak et al. - 1997
269   Multiscalar processors - Sohi, Breach et al. - 1995
251   Simultaneous multithreading: Maximizing on-chip parallelism - Tullsen, Eggers et al. - 1995
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214   Combining Branch Predictors - McFarling - 1993
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158   Effective compiler support for predicated execution using th.. - Mahlke, Lin et al. - 1992
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151   Baring it all to software: Raw machines - Waingold, Taylor et al. - 1997
150   An efficient algorithm for exploiting multiple arithmetic un.. (context) - Tomasulo - 1967
133   Fine-grain parallelism with minimal hardware support: A comp.. - Culler, Sah et al. - 1991
121   Monsoon: An explicit token-store architecture (context) - Papadopoulos, Culler - 1990
117   Clock rate versus IPC: The end of the road for conventional .. - Agarwal, Hrishikesh et al. - 2000
102   Dynamic speculation and synchronization of data dependences - Moshovos, Breach et al. - 1997
97   The case for a single-chip multiprocessor (context) - Olukotun, Nayfeh et al. - 1996
75   Measuring parallelism in computation-intensive scientific/en.. (context) - Kumar - 1988
74   Speculative versioning cache - Gopal, Vijaykumar et al. - 1998
74   Dataflow supercomputers (context) - Dennis - 1980
71   Space-time scheduling of instruction-level parallelism on a .. - Lee - 1998
71   First version data flow procedure language (context) - Dennis - 1991
69   Executing a program on the mit tagged-token dataflow archite.. (context) - Arvind - 1990
67   ARB: a hardware mechanism for dynamic reordering of memory r.. - Franklin, Sohi - 1996
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49   An economical solution to the cache coherence problem (context) - Archibald, Baer - 1984
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37   Look-ahead processors (context) - Keller - 1975
36   A design space evaluation of grid processor architectures - Nagarajan, Sankaralingam et al. - 2001
32   Cache design in the tightly coupled multiprocessor system (context) - Tang - 1976
27   A preliminary architecture for a basic dataflow processor (context) - Dennis - 1975
25   RISC i: A reduced instruction set vlsi computer (context) - Patterson, Sequin - 1981
25   The parallel programming language id and its compilation for.. (context) - Nikhil - 1990
21   Nanofabrics: Spatial computing using molecular electronics - Goldstein, Budiu - 2001
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12   Safetynet: improving the availability of shared memory multi.. - Sorin, Martin et al. - 2002
10   The program dependence web: a representation supporting cont.. (context) - Ottenstein, Ballance et al. - 1990
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8   The epsilon dataflow processor (context) - Grafe, Davidson et al. - 1989
8   Evaluation of a prototype data flow processor of the sigma-1.. (context) - Shimada, Hiraki et al. - 1986
8   The raw compiler project - Agarwal, Amarasinghe et al. - 1997
7   Lucid, a nonprocedural language with iteration (context) - Ashcroft, Wadge - 1977
7   The val language: Description and analysis (context) - McGraw - 1982
6   The optimal logic depth per pipeline stage is 6 to 8 fo4 inv.. (context) - Hrishikesh, Burger et al. - 2002
5   The optimal useful logic depth per pipeline stage is 6-8 fo4 (context) - Hrishikesh, Jouppi et al. - 2002
4   The architecture and system method of ddm1: A recursively st.. (context) - Davis - 1978
4   Using an oracle to measure potential parallelism in single i.. (context) - Nicolau, Fisher - 1981
4   The Misconstrued Semicolon: Reconciling Imperative Languages.. (context) - Veen - 1980
3   The fool programming language: Integrating single-assignment.. (context) - Murer, Marti - 1992
3   IMAGINE: Signal and image processing using streams (context) - Khailany, Dally et al. - 2000
3   Dddp-a distributed data driven processor (context) - Kishi, Yasuhara et al. - 1983
3   chip 3mb subarray based 3rd level cache on an itanium microp.. (context) - Weiss, Wuu et al. - 2002
3   An evaluation of speculative instruction execution on simult.. (context) - Swanson, McDowell et al. - 2002
2   Introduction: Special issue on microprocessor verification (context) - Hunt - 2002
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2   A flow analysis procedure for the translation of high-level .. (context) - Allan, Oldehoeft - 1980
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