This paper gives an overview of research efforts concentrating on developing ISA (Instruction Set Architecture) extensions on general-purpose workstation and desktop processors. Two major trends are increasing utilization of data-level parallelism in twodimensional data processing and increasing the number of operations executed per one instruction to obtain more complex functionality. Several studies show speed-ups ranging from 1.1 to 2.5 for complete applications compared to current ISA extensions.
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1253
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The Simplescalar toolset, version 2.0
– Burger, Austin
- 1997
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103
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Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
– Brooks, Martonosi
- 1999
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55
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Chimaera: A HighPerformance Architecture with a Tightly-Coupled Reconfigurable Functional Unit
– Ye, Moshovos, et al.
- 2000
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53
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Exploiting superword level parallelism with multimedia instruction sets
– Larsen, Amarasinghe
- 2000
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36
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Multimedia extensions for general-purpose processors
– Lee
- 1997
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17
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Fast subword permutation instructions using omega and flip network stages
– Yang, Lee
- 2000
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15
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The MOLEN rm-coded Processor
– Vassiliadis, Wong, et al.
- 2001
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12
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Subword Permutation Instructions for Two-Dimensional Multimedia Processing
– Lee
- 2000
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6
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On the efficiency of reductions in micro-SIMD media extensions
– Corbal, Espasa, et al.
- 2001
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6
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Multimedia Instruction Sets for General Purpose Microprocessors: A Survey
– Slingerland, Smith
- 2000
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4
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The long and winding road to highperformance image processing with MMX/SSE
– Conte, Tommesani, et al.
- 2000
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4
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A Survey of Media Processing Approaches
– Dasu, Panchanathan
- 2002
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4
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Overview of Research Efforts on Media ISA Extensions and their Usage in Video Coding
– Lappalainen, Hämäläinen, et al.
- 2002
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4
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Refining Instruction Set Architecture for High-Performance Multimedia Processing
– Lee, Fiskiran, et al.
- 2002
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4
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et al. Performance of image and video processing with general-purpose processors and media ISA extensions
– Ranganathan
- 1999
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3
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Architectures for the sum of absolute differences operation
– Guevorkian, Launiainen, et al.
- 2002
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3
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Exploring the Limits of Sub-Word Level Parallelism
– Scott, Davidson
- 2000
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3
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Performance Analysis of Instruction Set Architecture Extensions for Multimedia
– Slingerland, Smith
- 2001
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2
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Exploitation of Parallelism in General Purpose Processor based Systems for Multimedia Applications
– Debes
- 2000
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1
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et al., "Exploiting a new level of DLP in multimedia applications
– Corbal
- 1999
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1
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et al., "DLP + TLP processors for the next generation of media workloads
– Corbal
- 2001
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1
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Multi-media extensions in superpipelined microarchitectures. A new case for SIMD processing
– Ferretti
- 2000
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1
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et al., "Implementation and Evaluation of the Complex Streamed Instruction Set
– Juurlink
- 2001
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1
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Kapasi et al., "Efficient Conditional Operations for Data-parallel Architectures
– J
- 2000
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1
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et al., "Imagine: Media Processing with Streams
– Khailany
- 2001
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1
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Oehring et al., "MPEG-2 video decompression on simultaneous multithreaded processors
– unknown authors
- 1999
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1
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CompilerControlled Caching
– Shin, Chame, et al.
- 2002
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1
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et al., "Vector instruction set support for conditional operations
– Smith
- 2000
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1
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et al., "Fast sub-word permutation instructions based on butterfly networks
– Yang
- 2000
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