Adam J. Elbirt  Home/Search
Context
Related
| uml.edu/aelbirt/INTRRPTS.pdf From: uml.edu/aelbirt/ (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This paper describes and evaluates the results obtained in implementing three methods of precise interrupts in pipeline processors - in-order instruction completion, the reorder buffer, and the reorder buffer with bypass paths. Due to the limited scope of this paper, two other methods of implementing precise interrupts - the history buffer and future file - are not investigated. An interrupt is defined as precise if all instructions before the program counter at the interrupt have finished... (Update)
Similar documents based on text: More All
1.2: On Precise Interrupts - Mayan Moudgilly Stamatis (1996) (Correct)
0.8: A Fast Interrupt Handling Scheme for VLIW Processors - Özer, Sathaye, Menezes.. (1998) (Correct)
0.7: A Rigorous Correctness Proof of a Tomasulo Scheduler.. - Kroening, Müller, Paul (Correct)
BibTeX entry: (Update)
@misc{ elbirt-precise,
author = "Adam J. Elbirt",
title = "Precise Interrupt Schemes for Pipelined Processors and a Recommendation
for Virtual Memory Processor Systems",
url = "citeseer.ist.psu.edu/553487.html" }
Citations (may not include all citations):1 Instruction Level Parallel Processing (context) - Vassiliadis - 1993
1 Implementing Interrupts in Pipelined Processors (context) - Smith, Pleszkun - 1988
Documents on the same site (http://faculty.uml.edu/aelbirt/): More
An FPGA Implementation and Performance Evaluation of.. - Elbirt, Yip, Chetwynd, .. (1999) (Correct)
An FPGA-Based Performance Evaluation of the AES Block.. - Elbirt, Yip, Chetwynd, .. (2001) (Correct)
Reconfigurable Computing For Symmetric-Key Algorithms - Elbirt (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC