Data l’importanza delle Macchine a Stati Finiti nell’hardware, sono stati sviluppati vari approcci alla loro sintesi, verifica, collaudo e diagnosi. Questo articolo presenta un approccio unificante, basato sulla rappresentazione delle funzioni booleane mediante Binary Decision Diagram (BDD) ed algoritmi di attraversamento simbolico dello spazio degli stati. I dati sperimentali sui circuiti usati in sede internazionale come casi di prova [BBKo89] ne dimostrano l’efficacia. 1
|
2483
|
Graph-based algorithms for Boolean function manipulation
– Bryant
- 1986
|
|
858
|
The sciences of the artificial
– Simon
- 1969
|
|
415
|
Symbolic model checking: 10 20 states and beyond
– Burch, Clarke, et al.
- 1992
|
|
290
|
Combinational Profiles of Sequential Benchmark Circuits
– BRGLEZ, BRYAN, et al.
- 1989
|
|
273
|
Switching and Finite Automata Theory
– Kohavi
- 1978
|
|
166
|
The High-Level Synthesis of Digital Systems
– McFarland, Parker, et al.
- 1990
|
|
103
|
A unified framework for the formal verification of sequential circuits
– COUDERT, MADRE
- 1990
|
|
102
|
Verification of sequential machines using boolean functional vectors
– Coudert, Berthet, et al.
- 1989
|
|
38
|
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
– ROTH, BOURICIUS, et al.
- 1967
|
|
36
|
The VLSI-programming language Tangram and its translation into handshake circuits
– Berkel, Kessels, et al.
- 1991
|
|
24
|
General design theory and a CAD system
– Yoshikawa
- 1981
|
|
21
|
standard VHDL language reference manual
– IEEE
- 1988
|
|
19
|
On the Verification of Sequential Machines at Differing Levels of Abstraction
– Devadas, Ma, et al.
- 1987
|
|
14
|
ATPG aspects of FSM verification
– Cho, Hachtel, et al.
- 1990
|
|
12
|
The design of communicating systems: a system engineering approach
– Koomen
- 1991
|
|
10
|
Cathedral-II: a silicon compiler for digital signal processing
– Man, Rabaey, et al.
- 1986
|
|
10
|
CIRCAL: a calculus for circuit description
– Milne
- 1983
|
|
7
|
Designing Logic Systems Using State Machines
– Clare
- 1973
|
|
5
|
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
– Bossen, Hong
- 1971
|
|
4
|
An efficient verifier for finite state machines
– Hwang, Newton
- 1991
|
|
3
|
D.D.: Translating system specifications to VHDL. EDAC'91
– Narayan, Vahid, et al.
- 1991
|
|
2
|
A new Timed Petri Nets model for hardware representation
– Buonanno, Morasca, et al.
- 1991
|
|
2
|
Verification of Synthesized Circuits at Register Transfer Level with Flow Graphs
– Feldbusch, Kumar
- 1991
|
|
2
|
Statecharts: a visual formalism for complete systems,” Science of computer programming
– Harel
- 1987
|
|
2
|
Spann: “Diagnosis of Single-Gate Failures in Combinational Circuits
– Hornbuckle, N
- 1969
|
|
2
|
A Compositional Semantics for Timed Petri Nets
– Maggiolo-Schettini, Winkowski
- 1990
|
|
2
|
Cho: “A New Approach to the Fault Location of Combinational Circuits
– Su, C
- 1972
|
|
2
|
The FSM network model for behavioral synthesis of controldominated machines
– Wolf
- 1990
|
|
1
|
der Star: “Macro Testing: Unifying
– Beenker, Eerdewijk, et al.
- 1986
|
|
1
|
Langages de Description de Systèmes Logiques
– Borrione
- 1981
|
|
1
|
Sonza Reorda: “A new model for improving symbolic
– Cabodi, Camurati, et al.
- 1992
|
|
1
|
Specification and verification of hardware systems using the Temporal Logic language
– Coen-Porisini, Morzenti, et al.
- 1991
|
|
1
|
Jong: “Data flow graphs: system specification with the most unrestricted semantics,” EDAC’91
– de
- 1991
|
|
1
|
Vortrag auf der GME-Fachtagung Microelektronik,” Baden-Baden (Fed. Rep
– Ruge
- 1991
|
|
1
|
Maggiolo-Schettini: “An Algebra of Processes
– Winkowski, A
- 1987
|
