Abstract:
The fast pratetyping of datapath intensive architectures--such as those used in high-performance, real-time systems in telecommunications, speech, video, and image processing--is inettective and time consuming at present. All example of this type of architecture appears in Figure 1, which shows an example of the datapath section of a Viterbi processor used in connected speech recognition. Because this processor demands extremely high tlrroughput, a classical bn Neumann style of architecture is not acceptable. In the Van Nanmann style,all operations are muitiplexed on a single-data general-purpose datapath, and the content of the controller largely determines functionality: In this processor, the small ratio of sampling frequency to clock frequency prohibits exten-sive operation multiplexing. Thus, the emphasis shifts from the control to the datapath section. As Figure I shows, the datapath is almost a direct representation of the computation graph, and each operator has dedicated hardware assigned to it. Extensive pipelining helps to meet the clocking requirements. The processor's
Citations
|
12
|
Retiming for scheduling
– Potkonjak, Rabaey
- 1990
|
|
1
|
Roermund et al., "A General Purpose Programmable Video Signal Processor
– Van
- 1989
|
|
1
|
PADDI: Programmable Arithmetic Devices For
– Chen, Rabaey
- 1990
|
|
1
|
A HigMevel Language aud Silicon Compiler for
– Hilfinger
- 1985
|
|
1
|
Design & Test of Computers, special issue on high-level synthesis of digital circuits,Vol.7. No 5,Oct
– IEZ'
- 1990
|
|
1
|
Shung et ah, "An Integrated CAD System for Algorithm-Speciiic IC Design," Proc. lnt'l Conf System Design,Jan
– unknown authors
- 1989
|
|
1
|
Jam et al.. "Module Selection for Pipelined Synthesis? Pros. Design Automation Con
– unknown authors
- 1988
|
|
1
|
Note el al., "Combined Hardware Selection and Pipelining in High-Performance Data-Path Design
– unknown authors
- 1990
|
|
1
|
Correlated Percolation and Repulsive Particle Systemsj
– Welsh
- 1984
|
|
1
|
A Transformational Model of JUNE 1991 VLSI Systolic Design
– Lam
- 1985
|
|
1
|
Breaking The Recursive BerrieneckS
– Messersclqmitt
- 1988
|
|
1
|
et al., "Scheduliig and Hardware Synthesis in Pipelined Datapaths
– Hwang
- 1989
|
|
1
|
int'l Con Computer Design
– Brayton
|
|
1
|
mpu ter-Atded Design. Voh CAD 6, No. 6, No 1987,pp 1()62-1081. Jan M. Rabaey is an associate professor at the University of California, Berkeley, where his mifin interests are in signal-processing architectures and the computer-aided analysis, synthesis,
– Co
|
