by Mustafa Badaroglu Tm, Kris Tiri, Stphane Donnay, Piet Wambacq, Ingrid Verbauwhede, Georges Gielen, Hugo De Man
http://www.ivgroup.ee.ucla.edu/pdf/2002clocktree.pdf
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Abstract:
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a nction of the clock skew. The experimental results show>x2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized.
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