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Abstract: Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We... (Update)
Context of citations to this paper: More
...for a read. In this paper, we assume that the buses are different and hence 4 cycle reads would be required without pre fetching. In [6], we introduced a technique, called pre fetching, for reducing the extra cycles. Pre fetching, similar to caching, keeps local copies of a...
.... data into register copies added to the wrapper in order to reduce or even eliminate the performance overhead associated with a wrapper [7][8] while still obeying the VCI standard. This approach involves adding register copies from the internals into the wrapper, and adding...
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BibTeX entry: (Update)
R. Lysecky, F. Vahid, T. Givargis, and R. Patel. Pre-fetching for Improved Core Interfacing. International Symposium on System Synthesis, 1999. http://citeseer.ist.psu.edu/article/lysecky99prefetching.html More
@inproceedings{ lysecky99prefetching,
author = "Roman L. Lysecky and Frank Vahid and Rilesh Patel and Tony Givargis",
title = "Pre-Fetching for Improved Core Interfacing",
booktitle = "{ISSS}",
pages = "51-55",
year = "1999",
url = "citeseer.ist.psu.edu/article/lysecky99prefetching.html" }
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http://www.mentorg.com/inventra/
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