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Abstract:

The high transistor density now possible with CMOS integrated circuits has made power dissipation an important design consideration. However, power dissipation in a logic cir-cuit is a function of the input vector or vector sequence applied. This makes accurate estimation of worst-case power dissipation extremely difficult, since the number of input sequences that have to be simulated in order to find the sequence that produces'the maximum power dissipation is exponential in the number of inputs to the circuit. In this paper we show that a simplified model of power dissipation relates maximizing dissipation to maximizing gate outpnt activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maxi-mizes the weighted activity, we give algorithms for transforming the problem to a weighted max-satisfiability problem, and then present exact and approximate algorithms for solving weighted max-satisfiability. That is, transformations are presented that convert a logic description into a multiple-output Boolean function of the input vector or vector sequence, wilere each output of the Boolean function is associated with a logic gate output transition. It then follows that an assignment to the input vector or vector sequence which results in a maximum weighted number of these function's outputs becoming 1 corresponds to the input vector or vector sequence causing maximum weighted activity. Algorithms for constructing the Booleau function for dynamic CMOS as well as for static CMOS, which take into account dissipation dne to glitching, are presented. Finally, we present efficient exact and approximate methods for solving the so generated weighted maxsatisfiability problem.

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