M. Kandemir* P. Banerjee* A. Choudhary* J. Ramanujam t E. Ayguad$  Home/Search
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Abstract: The delivered performance on modern processors that employ deep memory hierarchies is closely related to the performance of the memory subsystem. Compiler optimizations aimed at improving cache locality are critical in realizing the performance potential of powerful processors. For scientific applications, several loop transformations have been shown to be useful in improving both temporal and spatial locality. Recently, there has been some work in the area of data layout optimizations, i.e.,... (Update)
Context of citations to this paper: More
...of cache misses with cache hints per access. tions, data layout optimizations or hardware or software prefetching schemes[22, 21, 15, 13]. Most of the hardware modi cations, loop transformations and data layout transformations aim at improving the cache locality of the...
...of cache misses with cache hints per access. tions, data layout optimizations or hardware or software prefetching schemes[22, 21, 15, 13]. Most of the hardware modifications, loop transformations and data layout transformations aim at improving the cache locality of the...
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BibTeX entry: (Update)
M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade. An integer linear programming approach for optimizing cache locality. In Proceedings of the 1999. http://citeseer.ist.psu.edu/article/kandemir99integer.html More
@inproceedings{ kandemir99integer,
author = "Mahmut T. Kandemir and Prithviraj Banerjee and Alok N. Choudhary and J. Ramanujam and Eduard Ayguade",
title = "An integer linear programming approach for optimizing cache locality",
booktitle = "International Conference on Supercomputing",
pages = "500-509",
year = "1999",
url = "citeseer.ist.psu.edu/article/kandemir99integer.html" }
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