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Abstract: We propose a worst case timing analysis technique for in-order, multiple-issue machines. In the proposed technique, timing information for each program construct is represented by a directed acyclic graph (DAG) that shows dependences among instructions in the program construct. From this information, we derive for each pair of instructions the distance bounds between their issue times. Using these distance bounds, we identify the sets of instructions that can be issued at the same time.... (Update)
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BibTeX entry: (Update)
S.-S. Lim, J. H. Han, J. Kim, and S. L. Min. A Worst Case Timing Analysis Technique for Multiple-Issue Processors. Technical Report SNU-CE-AN-98-001, Architecture and Network Laboratory, Seoul National University, 1998. http://citeseer.ist.psu.edu/article/lim98worst.html More
@inproceedings{ lim98worst,
author = "Sung-Soo Lim and Jung Hee Han and Jihong Kim and Sang Lyul Min",
title = "A Worst Case Timing Analysis Technique for Multiple-Issue Machines",
booktitle = "{RTSS}",
pages = "334-345",
year = "1998",
url = "citeseer.ist.psu.edu/article/lim98worst.html" }
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