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Abstract: Gi-Hong Im Lucent Bell Laboratories 200 Laurel Avenue Middletown, NJ-07748 ph(908)957-7334 igh mtdcr. mt.lucent.com Presented in this paper are: 1.) system design issues for the implementation of 51.84 Mb/s ATM-LAN and broadband access transceivers, and 2.) a pipelined fractionally-spaced linear equalizer (FSLE) architecture. Algorithmic concerns such as signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints such as power dissipation, area, and speed, were... (Update)
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BibTeX entry: (Update)
@misc{ shanbhag-vlsi,
author = "Naresh R. Shanbhag",
title = "VLSI Systems Design of 51.84 Mb/s Transceivers for ATM-LAN and Broadband
Access",
url = "citeseer.ist.psu.edu/516610.html" }
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18 Pipelined Adaptive Digital Filters (context) - Shanbhag, Parhi - 1994
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7 Relaxed Look-ahead pipelined LMS adaptive filters and their .. (context) - Shanbhag, Parhi - 1993
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4 Transmitter design for data transmission in the presence of .. (context) - Golden, Mazo et al. - 1995
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2 51.84 Mb/s 16-CAP ATM LAN Standard (context) - Im, Harman et al. - 1995
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1 A pipelined VLSI NEXT cancellet for premises applications (context) - Im, Shanbhag
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1 Local distribution for interactive multimedia TV (context) - Harman, Huang et al. - 1995
1 Finite-precision analysis of the pipelined ADPCM coder (context) - Shanbhag, Parhi - 1994
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