(Enter summary)
Abstract: This dissertation examines the performance difference between invalidate-based
and update-based cache coherence protocols for scalable shared-memory multiprocessors.
The first portion of the dissertation reviews cache coherence. First, chapter 1 describes
the cache coherence problem and identifies the two classes of cache coherence
protocols, invalidate-based and update-based. The chapter also reviews bus-based
protocols and reviews the additional requirements placed on the protocols to extend... (Update)
Context of citations to this paper: More
.... well as a cost savings [95] most studies conclude that centralized protocols perform as well as or better than distributed protocols [35, 37, 44]. In our experiments, we only consider fully mapped centralized protocols. The coherence protocol used in this study is similar to...
Cited by: More
Communication Mechanisms in Shared Memory Multiprocessors - Byrd (1998)
(Correct)
Active bibliography (related documents): More All
0.8: Update-Based Cache Coherence Protocols For Scalable.. - Glasco, Delagi, Flynn (1993)
(Correct)
0.7: Extending The Scalable Coherent Interface For Large-Scale.. - Johnson (1993)
(Correct)
0.7: Write Grouping For Update-Based Cache Coherence Protocols - Glasco, Delagi, Flynn (1994)
(Correct)
Similar documents based on text: More All
1.7: Design and Analysis of Update-Based Cache Coherence Protocols for .. - Glasco (1995)
(Correct)
0.9: Trace-Driven Simulation of Data-Alignment and other Factors .. - Markatos, Chronaki (1994)
(Correct)
0.7: Evaluating the Impact of Coherence Protocols on Parallel.. - Costa, Bianchini, Dutra (1996)
(Correct)
BibTeX entry: (Update)
David Brian Glasco. Design and Analysis of Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors. PhD thesis, Stanford University, 1995. http://citeseer.ist.psu.edu/article/glasco95design.html More
@techreport{ glasco95design,
author = "David Brian Glasco",
title = "Design and Analysis of Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors",
number = "CSL-TR-95-670",
pages = "209",
year = "1995",
url = "citeseer.ist.psu.edu/article/glasco95design.html" }
Citations (may not include all citations):
606
How to Make a Multiprocessor Computer That Correctly Execute.. (context) - Lamport - 1979
462
Deadlock-Free Message Routing in Multiprocessor Interconnect.. (context) - Dally, Seitz - 1987 ACM DBLP
373
Clocks and the Ordering of Events in a Distributed System (context) - Lamport - 1978
367
Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1990 ACM
362
The Stanford FLASH Multiprocessor (context) - Kuskin, Ofelt et al. - 1994
357
The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990 ACM DBLP
249
Tolerating Latency Through SoftwareControlled Prefetching in..
- Mowry, Gupta - 1991
234
Competitive Snoopy Caching (context) - Karlin, Manasse et al. - 1984 DBLP
213
Weak Ordering - A New Definition
- Adve, Hill - 1990 DBLP
195
A New Solution to Coherence Problems in Multicache Systems (context) - Censier, Feautrier - 1978 ACM DBLP
173
Protocol Verification as a Hardware Design Aid
- Dill, Drexler et al. - 1992
170
LimitLESS Directories: A Scalable Cache Coherence Scheme
- Chaiken, Kubiatowicz et al. - 1991 ACM DBLP
165
Memory Access Buffering in Multiprocessors (context) - Dubois, Scheurich et al. - 1986 ACM DBLP
157
Architecture and Application of the HEP Multiprocessor Compu.. (context) - Smith - 1981
156
An Evaluation of Directory Schemes for Cache Coherence
- Agarwal, Simoni et al. - 1988 ACM DBLP
145
DDM - A Cache-Only Memory Architecture
- Hagersten, Landin et al. - 1992 ACM DBLP
138
SPLASH Stanford Parallel Applications for Shared-Memory (context) - Singh, Weber et al. - 1992
130
Memory Consistency and Event Ordering in Scalable Shared-Mem.. (context) - Gharachorloo, Lenoski et al. - 1990 ACM DBLP
122
Firefly: A Multiprocessor Workstation (context) - Thacker, Stewart et al. - 1987 ACM DBLP
113
DirectoryBased Cache-Coherence in Large-Scale Multiprocessor.. (context) - Chaiken, Fields et al. - 1990
111
Using Cache Memory to Reduce Processor-Memory Traffic (context) - Goodman - 1983 ACM DBLP
101
Better Verification Through Symmetry
- Ip, Dill - 1993 ACM DBLP
96
A Characterization of Sharing in Parallel Programs and its A.. (context) - Eggers, Katz - 1988 ACM DBLP
88
A Survey of Cache Coherence Schemes for Multiprocessors (context) - Stenstrom - 1990 ACM DBLP
82
A Low Overhead Coherence Solution for Multiprocessors with P.. (context) - Papamarcos, Patel - 1984
70
Cache Memories (context) - Smith - 1982 ACM DBLP
60
KSR1 Principles of Operation (context) - Research, MA - 1991
55
Memory Access Dependencies in Shared-Memory Multiprocessors (context) - Dubois, Scheurich - 1990 ACM DBLP
51
Reducing Memory and Traffic Requirements for Scalable Direct..
- Gupta, Weber et al. - 1990 DBLP
51
Anatomy of a Message in the Alewife Multiprocessor
- Kubiatowicz, Agarwal - 1993 ACM DBLP
48
Evaluating the Performance of Four Snooping Cache Coherence .. (context) - Eggers, Katz - 1989
46
Architecture of a message-driven processor (context) - Dally - 1987
39
Exploiting Heterogeneous Parallelism on a Multithreaded Mult.. (context) - Alverson, Alverson et al. - 1991 ACM DBLP
36
An Empirical Evaluation of Two Memory-Efficient Directory Me.. (context) - O'Krafka, Newton - 1990 ACM DBLP
36
Cache Coherence Protocols: Evaluation Using a Multiprocessor.. (context) - Archibald, Baer - 1986 ACM DBLP
35
Hiding Shared Memory Reference Latency on the Galactica Net .. (context) - Jr, Jr - 1992 DBLP
34
Scalable Coherent Interface (context) - James, Laundrie et al. - 1990 ACM
30
Parallel Implementation of Multifrontal Schemes (context) - Duff - 1986 ACM
27
Wire-Efficient VLSI Multiprocessors Communication Networks (context) - Dally - 1987
25
The Dragon Computer System: An Early Overview (context) - McCreight - 1984
24
Design Decisions in SPUR (context) - Hill - 1986 ACM
23
Users' Guide for the HarwellBoeing Sparse Matrix Collection
- Duff, Grimes et al. - 1988
22
The Cache Coherence Problems in Shared-Memory Multiprocessor.. (context) - Archibald - 1987
22
Efficient Verification of Symmetric Concurrent Systems
- Ip, Dill - 1993
14
Dynamic Pointer Allocation for Scalable Cache Coherence Dire..
- Simoni, Horowitz - 1991
13
The Performance of Cache-Coherent RingBased Multiprocessors
- Barroso, Dubois - 1993
12
Tightly Coupled Multiprocessor Systems Speeds Memory-Access .. (context) - Frank - 1984
12
Design of an Adaptive Cache Coherence Protocol for Large Sca.. (context) - Yang, Thangadurai et al. - 1992 ACM DBLP
11
Update-Based Cache Coherence Protocols for Scalable Shared-M..
- Glasco, Delagi et al. - 1994 ACM DBLP
10
Low-Cost Support for Fine-Grain Synchronization in Multiproc..
- Kranz, Lim et al. - 1992 ACM
10
Lockup-Free Caches in High-Performance Multiprocessors (context) - Scheurich, Dubois - 1991 ACM DBLP
7
A Comparative Evaluation of Nodal and Supernodal Parallel Sp.. (context) - Rothberg, Gupta - 1990 ACM
4
Cache Coherence for Scalable Shared Memory Multiprocessors (context) - Thapar - 1992 ACM
4
A Write Update Cache Coherence Protocol for MIN-Based Multip.. (context) - Algudady, Das et al. - 1990
4
The Impact of Cache Coherence Protocols on Systems Using Fin.. (context) - Glasco, Delagi et al. - 1994 ACM DBLP
4
Performance Evaluation of Memory Consistency Models for Shar..
- Gharachorloo, Gupta et al. - 1991 ACM
4
Kendall Square Multiprocessor: Early Experience and Performa..
- Dunigan
4
NASA Ames Research Center (context) - Bailey, Barton et al. - 1991
4
Instrumented Architectural Simulation (context) - Delagi, Saraiya et al. - 1988 ACM
3
Scalable Shared-Memory Multiprocessor Architectures (context) - Thakkar, Dubois et al. - 1990 ACM DBLP
3
Linked List Cache Coherence for Scalable Shared Memory Multi.. (context) - Thapar, Delagi et al. - 1993 DBLP
3
An Evaluation of Cache Coherence Protocols for MIN-Based Mul.. (context) - Baylor, McAuliffe et al. - 1989
2
Write Grouping for Update-Based Cache Coherence Protocols
- Glasco, Delagi et al. - 1994
1
Physical and Cache Coherence Specifications (context) - Department, Lane et al. - 1991
1
SimpleCare Instrumented Simulator Multiprocessor Architectur.. (context) - Bruce, Sayuri et al. - 1990
1
Mur' Annotated Reference Manual (context) - Drexler, Ip - 1992
1
Revision to Memory Consistency and Event Ordering in Scalabl.. (context) - Gharachorloo, Gupta et al. - 1993
1
APRIL: A Processor Architecture for Mutltiprocessing (context) - Agarwal, Lim et al. - 1990
1
Numerical Analysis (context) - Elden, Wittmery-Koch - 1990 ACM
1
Analysis of Directory Based Cache Coherence Schemes with Mul.. (context) - Nanda, Jiang - 1992 ACM DBLP
1
Technical Report Computer Sciences (context) - Goodman, Sequential - 1991
1
Limits on Network Performance or Moderate Dimensions are Bet.. (context) - Agarwal - 1991
Documents on the same site (http://arithmetic.stanford.edu/techrep.html): More
On Division And Reciprocal Caches - Stuart Oberman (1995)
(Correct)
The Design And Implementation Of A High-Performance.. - Oberman, Quach, Flynn (1994)
(Correct)
A Comparison of Hardware Prefetching Techniques for.. - Zucker, Flynn, Lee (1995)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC