The high throughput computation requirements of real-time digital signal processing (dsp) systems usually dictate hardware intensive solutions. Often attendant to hardware approaches are problems of high development costs, slow turnaround, susceptibility to errors, and difficulty in testing and debugging, all of which tend to inhibit the rapid implementation of such systems. Research is underway into the synthesis of application specific hardware to aid the system designer by automatically generating hardware that is "correct by construction". The creation of configurable, pre-fabricated hardware that has been designed for high speed computations forms part of this research and is the main topic of this thesis. This work contains a survey of some typical real-time dsp algorithms drawn from video and speech processing and summarizes the particular computation challenges posed by this class of algorithms. Currently available hardware choices and their trade-offs and limitations are discussed. A multiprocessor architecture consisting of programmable arithmetic devices is presented as a novel platform for supporting high speed digital signal processing. The vlsi realization of the architecture and an accompanying software development environment are presented as a proof of concept. The main conclusion of this work is that software-configurable hardware approaches to high speed digital signal processing problems form viable alternatives to existing approaches, for systems designers interested in rapidly prototyping or implementing their ideas.
|
2172
|
Optimization by simulated annealing
– Kirkpatrick, Gelatt, et al.
- 1983
|
|
160
|
Why systolic architectures
– Kung
- 1982
|
|
126
|
Optimizing synchronous systems
– Leiserson, Saxe
- 1983
|
|
121
|
VLSI array processors
– KUNG
- 1988
|
|
113
|
Some Computer Organizations and Their Effectiveness
– Flynn
- 1972
|
|
102
|
Mips Risc Architecture
– Kane, Heinrich
- 1991
|
|
102
|
Fast prototyping of data path intensive architecture
– Rabaey, Chu, et al.
- 1991
|
|
52
|
Trends in cellular and cordless communication
– Goodman
- 1991
|
|
45
|
IRSIM: An incremental MOS switch-level simulator,” in Proc. 26th Design Auromution Cont
– Salz, Horowitz
- 1989
|
|
42
|
Technology Mapping of Lookup Table-Based FPGAs for Performance
– Francis, Rose, et al.
- 1991
|
|
41
|
Tutorial on highlevel synthesis
– McFarland, Parker, et al.
- 1988
|
|
41
|
Concurrent vlsi architectures
– Seitz
- 1984
|
|
33
|
Magic: A VLSI layout system
– Ousterhout, Hamachi
- 1984
|
|
32
|
A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths
– Chen, Rabaey
- 1992
|
|
32
|
Very high speed computing systems
– Flynn
- 1966
|
|
30
|
FIamel: A High-Level Hardware Compiler
– Trickey
- 1987
|
|
28
|
Logic Synthesis for Programmable Gate Arrays
– Murgai, Nishizaki, et al.
- 1990
|
|
26
|
PHIDEO: a silicon compiler for high speed algorithms
– Lippens, Meerbergen, et al.
- 1991
|
|
22
|
Third-generation architecture boosts speed and density of field-programmable gate arrays
– Hsieh
- 1990
|
|
22
|
Programmable DSP Architectures: Part I
– Lee
- 1988
|
|
22
|
A High-level Language and Silicon Compiler for Digital Signal Processing
– Hilfinger
- 1985
|
|
22
|
Rapid-Prototyping of Hardware and Software in a Unified Framework
– Srivastava, Broderson
- 1991
|
|
19
|
HYPER: An interactive synthesis environment for high performance real time applications
– Chu, Potkonjak, et al.
- 1989
|
|
17
|
A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs
– Potkonjak, Rabaey
- 1989
|
|
15
|
Simulation Program with Integrated Circuit Emphasis
– Nagel, Pederson
- 1973
|
|
14
|
The implementation of hardware subroutines on field programmable gate arrays
– Hastie, Cliff
- 1990
|
|
14
|
Architectural partitioning for system level design
– Lagnese, Thomas
- 1989
|
|
13
|
VLSI Theory and Parallel Supercomputing
– Leiserson
- 1989
|
|
12
|
Configurable hardware: A new paradigm for computation
– Gray, Kean
- 1989
|
|
9
|
A data-flow processor for real-time low-level image processing
– Qu'enot, Zavidovique
- 1991
|
|
8
|
MIS: A multiple level logic optimization system
– Brayton
- 1987
|
|
8
|
A second generation user-programmable gate array
– Hsieh, Duong, et al.
- 1987
|
|
8
|
A Taxonomy for Computer Architectures
– Skillicorn
- 1988
|
|
8
|
VLSI programming and silicon compilation
– Berkel, Niessen, et al.
- 1988
|
|
8
|
The White Dwarf: A High-Performance Application-Specific Processor
– Wolfe, Breternitz, et al.
- 1988
|
|
7
|
An FPGA Family Optimized for High Densities and Reduced Routing Delay
– Ahrens
- 1990
|
|
7
|
Algorithms and Architectures for Machine Vision
– Blanz, Petkovic, et al.
- 1989
|
|
7
|
The Challenges of Digital HDTV
– Jurgen
- 1991
|
|
7
|
Architectures and Design Techniques for Real-Time Image-Processing IC's
– Ruetz, Brodersen
- 1987
|
|
7
|
A Reconfigurable Data Driven Multi-Processor Architecture for Rapid Prototyping
– Yeung, Rabaey
- 1993
|
|
5
|
BORG: A Reconfigurable Prototyping Board Using Field-Programmable Gate Arrays
– Chan, Schlag, et al.
- 1992
|
|
5
|
A compiler for multiprocessor DSP implementation
– Hoang, Rabaey
- 1992
|
|
4
|
User-Programmable Gate Arrays
– Freeman
- 1988
|
|
4
|
A 300 MOPS Video Signal Processor with a Parallel Architecture
– Minami, Kasai, et al.
- 1991
|
|
4
|
Resource Driven Synthesis
– Rabaey, Potkonjak
- 1990
|
|
4
|
Cathedral-II: A Synthesis System for Multiprocessor DSP Systems
– Rabaey, DeMan, et al.
- 1988
|
|
4
|
SIERA: A CAD Environment for Real-TIme Systems
– Sun, Srivastava, et al.
- 1991
|
|
4
|
A real-time video signal processor suitable for motion picture coding applications
– Tamitani, Harasaki, et al.
- 1989
|
|
3
|
Three Competing Design Methodologies for ASIC's: Architectural Synthesis, Logic Synthesis and Module Generation
– Keutzer
- 1989
|
|
3
|
Automated synthesis of a high speed CORDIC algorithm with the Cathedral-III compilation system
– unknown authors
- 1988
|