Chih-Kong Ken Yang  Home/Search
Context Related
| stanford.edu/group/../...cky_thesis.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: stanford.edu/group/people (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Demand for bandwidth in serial links has been increasing as the communications industry demand higher quantity and quality of information. Whereas traditional gigabit per second links has been in bipolar or GaAs, this research aims to push the use of CMOS process technology in such links. Intrinsic gate speed limitations are overcome by parallelizing the data. The on-chip frequency is maintained at a fraction (1/16) of the offchip data rate. Clocks with carefully controlled phases tapped from a ... (Update)
Context of citations to this paper: More
.... of a typical transceiver architecture and the fanout of 4 gate delay metric that is used to normalize circuit speed across CMOS processes [11][44] This discussion is followed by an analysis of link performance that derives the number of bits a link can transport from the peak...
.... by the minimum cycle time required to sustain a full swing signal through a inverter buffer chain required for clock distribution [51]. Simulated data, plotted in Figure 4.3, presents the normalized signal magnitude of a clock signal at the output of a 6 stage inverter...
Cited by: More
A Framework For Designing Reusable Analog Circuits - And The Committee (Correct)
Precision CMOS Receivers for VLSI Testing Applications - Weinlader (2001) (Correct)
Energy-Efficient I/o Interface Design with Adaptive Power-Supply.. - Wei (2001) (Correct)
Active bibliography (related documents): More All
5.0: High Performance Inter-Chip Signalling - Sidiropoulos (1998) (Correct)
4.2: High Speed Electrical Signalling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998) (Correct)
3.3: High-Speed Electrical Signaling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998) (Correct)
Similar documents based on text: More All
0.5: A 0.8μm CMOS 2.5Gbps Oversampling Receiver for Serial Links - Yang, Horowitz (1996) (Correct)
0.4: A 0.5-µm CMOS 4.0-Gbit/s Serial Link Transceiver with.. - Yang, Farjad-Rad.. (1998) (Correct)
0.4: A 0.8-μm CMOS 2.5 Gb/s Oversampling Receiver and.. - Yang, Horowitz (1996) (Correct)
Related documents from co-citation: More All
4: Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques (context) - Maneatis - 1996
3: Digital Systems Engineering (context) - Dally, Pulton - 1998
3: A semi-digital dual delay locked loop - Sidiropoulos, Horowitz - 1997
BibTeX entry: (Update)
C.K.K. Yang, "Design of High-speed Serial Links in CMOS", PhD Dissertation, http://citeseer.ist.psu.edu/article/yang98design.html More
@techreport{ yang98design,
author = "Chih-Kong Ken Yang",
title = "Design of High-Speed Serial Links in {CMOS}",
number = "CSL-TR-98-775",
pages = "181",
year = "1998",
url = "citeseer.ist.psu.edu/article/yang98design.html" }
Citations (may not include all citations):362 The Stanford FLASH Multiprocessor (context) - Kuskin - 1994
159 Principles of CMOS VLSI Design A Systems Perspective (context) - Weste, Eshraghian - 1993
61 Matching Properties of MOS Transistors (context) - Pelgrom - 1989
46 Communication Systems Engineering (context) - Proakis, Salehi - 1994
44 Phase Lock Techniques (context) - Gardner - 1979
40 Spider: a high-speed network interconnect (context) - Galles - 1997
31 Precise delay generation using coupled oscillators - Maneatis - 1993
26 Low-jitter process-independent DLL and PLL based on selfbias.. (context) - Maneatis - 1996
23 A variable delay line PLL for CPU-coprocessor synchronizatio.. (context) - Johnson - 1988
23 A General Theory of Phase Noise in Electrical Oscillators - Hajimiri, Lee - 1998
19 A Semidigital Dual Delay-Locked Loop - Sidiropoulos, Horowitz - 1997
18 Charge-pump phase-lock loops (context) - Gardner - 1980
16 Integrated Analog-to-Digital and Digital-to-Analog Converter.. (context) - Plassche - 1994
15 Automatic Impedance Control (context) - DeHon, Jr et al. - 1993
15 A PLL clock generator with 5 to 110 MHz lock range for micro.. (context) - Young - 1992
15 Transmission lines for digital and communication networks 3r.. (context) - Matick - 1997
13 Design of PLL-based clock generation circuits (context) - Jeong - 1987
11 Jitter in Ring Oscillators (context) - McNeill - 1997
11 A unified single-phase clocking scheme for VLSI systems (context) - Afghahi - 1990
10 Phase-Locked Loops (context) - Best - 1997
9 A CMOS serial link for fully duplexed data communication (context) - Lee - 1995
9 A 1.0625 Gbps transceiver with 2x-oversampling and transmit .. (context) - Fiedler
9 Monolithic Phase Locked Loops and Clock Recovery Circuits (context) - Razavi - 1996
8 A Sampling Technique and Its CMOS Implementation with 1-Gb/ .. (context) - Gray - 1994
7 A wide-bandwidth low-voltage PLL for PowerPC microprocessors (context) - Alvarez - 1995
6 Experimental study of threshold voltage fluctuation due to s.. (context) - Mizuno - 1994
6 Technical Aspects of Data Communication (context) - McNamara - 1982
6 A 660-MB/s interface megacell portable circuit in 0.3-m0. 7-.. (context) - Donnelly
5 The delay vernier pattern generation technique (context) - Moyer - 1997
5 A DC-Balanced Partitioned-Block 8B/10B Transmission Code (context) - Widmer, Franaszek - 1983
5 A 100-MHz pipelined CMOS comparator (context) - Wu - 1988
5 An 800Mbps Multi-Channel CMOS Serial Link with 3x Oversampli.. (context) - Kim
5 A 155MHz Clock Recovery Delay-and Phase-Locked Loop (context) - Lee, Bulzachelli - 1992
5 A 0.8-m CMOS 2.5 Gb/s oversampling receiver and transmitter .. (context) - Yang - 1996
4 Predicting CMOS Speed with Gate Oxide and Voltage Scaling an.. (context) - Chen
4 A monolithic 480 Mb/s parallel AGC/decision/clock-recovery c.. (context) - Hu - 1993
4 A 1-Gb/s, four-state, sliding block Viterbi decoder (context) - Black - 1997
4 A 0.6-m CMOS 4 Gbps Transceiver with Data Recovery using Ove.. (context) - Yang
4 Transmitter equalization for 4-Gbps signaling (context) - Dally - 1997
4 Design and Characterization of a CMOS Off-Chip Driver/ Recei.. (context) - Hanafi - 1992
3 A 30-MHz hybrid analog/digital clock recovery circuit in 2-m.. (context) - Kim - 1990
3 A 500-megabyte/s data-rate 4.5 M DRAM (context) - Kushiyama - 1993
3 A second-generation modem analog front-end (context) - Combe
3 A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s D.. (context) - Lee - 1994
3 Single-Chip 1062MBaud CMOS Transceiver for Serial Data Commu.. (context) - Ewen
3 NMOS IC's for Clock and Data Regeneration in Gigabitper -Sec.. (context) - Enam, Abidi
3 A CMOS Gate Array with 600 Mb/s Simultaneous Bidirectional I.. (context) - Takahashi - 1995
3 Work progresses on gigabit Ethernet (context) - Thompson - 1997
3 A CMOS 8-bit high speed A/D converter IC (context) - Yukawa - 1988
3 The facts about FireWire [serial communication bus (context) - Wickelgren - 1997
3 Semiconductor Memories: A Handbook of Design (context) - Prince - 1991
3 A 320 MHz CMOS Triple 8 bit DAC with PLL (context) - Reynolds - 1994
3 A 900 Mb/s bidirectional signaling scheme (context) - Mooney - 1995
3 A Novel High Speed Ring Oscillator for Multi-Phase Clock Gen.. (context) - Lee, Kim et al. - 1997
3 Optimization of Phase-Locked Loop Performance in Data Recove.. (context) - Co, Jr - 1994
3 A 700-Mb/s/pin CMOS signaling interface using current integr.. (context) - Sidiropoulos - 1997
3 Metastability in CMOS library elements in reduced supply and.. (context) - Portmann - 1995
3 NRZ timing recovery technique for band limited channels (context) - Song - 1996
3 PLL Design for a 500MB/s Interface (context) - Horowitz
2 A CMOS 500 Mbps/pin synchronous point to point link interfac.. (context) - Sidiropoulos - 1994
2 Sizing an Inverter with a Precise Delay: Generation of Compl.. (context) - Argade - 1989
2 A CMOS Analog Front-End Circuit for an FDM-Based ADSL System (context) - Chang - 1995
2 A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Loc.. (context) - Banu, Dunlop - 1993
2 A Single-Chip 266Mb/s CMOS Transmitter/Receiver for Serial D.. (context) - Chen, Waldron
2 An Integrated High Resolution CMOS Timing Generator Based on.. (context) - Christiansen
2 An analog front end for multi-standard power line carrier mo.. (context) - Boxho
2 CMOS Gigabit-per-Second Switching (context) - Cooperman, Andrade - 1993
2 High Speed Generation of Maximal Length Sequences (context) - Lempel, Eastman - 1971
2 A Burst mode, Packet Receiver with Precision Reset and Autom.. (context) - Swartz - 1994
2 Single-chip 4*500-MBd CMOS transceiver (context) - Widmer
2 Clock/Data Recovery PLL Using Half-Frequency Clock (context) - Rau - 1997
2 Design Techniques for High-Speed, High-Resolution Comparator.. (context) - Razavi, Wooley
1 3.5-Gb/s x 4-Ch Si bipolar LSI's for Optical Interconnection.. (context) - Ishihara - 1995
1 A 1.5-Gb/s link interface chipset for computer data transmis.. (context) - Walker - 1991
1 A Tracking Clock Recovery Receiver for 4-Gb/s Signaling (context) - Poulton - 1997
1 Multichannel Parallel Data Link for Optical Communication (context) - Ota, Swartz - 1991
1 Silicon Bipolar Chipset for SONET/SDH 10 Gb/s FiberOptic Com.. (context) - Andersson - 1995
1 A Si Bipolar 5-Gb/s 8:1 Multiplexer and 4.2-Gb/s 1:8 Demulti.. (context) - Ohuchi - 1992
1 A 6-Gbps CMOS Phase Detectig DEMUX Module Using Half-Frequen.. (context) - Nakamura
1 A Dynamic Line-Termination Circuit for Multireceiver Nets (context) - Dolle - 1996
1 High-Speed CMOS I/O Buffer Circuits (context) - Ishibe - 1992
1 Digital Burst Mode Clock Recovery Technique for FiberOptic S.. (context) - Eldering - 1994
1 MECL Data Book (context) - Inc
1 Serial-to-Parallel Transformation of Linear-Feedback Shift-R.. (context) - Hsiao, Sih - 1968
1 An Equalization Scheme for 10-Gb/s 4-PAM Signaling over Long.. (context) - Farjad-Rad - 1997
1 CORD - A WDM Optical Network: Control Mechanism Using Subcar.. (context) - Cerisola - 1995
1 Memory- fast interfaced for DRAMs (context) - Foss
1 Low Power GaAs Current-Mode 1.2Gb/s Interchip Interconnectio.. (context) - Long, Zhang - 1997
1 GTL: a low-swing solution for high-speed digital logic (context) - Ammar, Ajouri - 1995
1 Optimization of the Latching Pulse for Dynamic Flip-Flop Sen.. (context) - Lynch, Boll - 1974
1 Prentice Hall 1988 Englewood Cliffs (context) - Sklar, Fundamentals - 1988
1 Design of a Low-Power 10Gb/s Si Bipolar 1:16 Demultiplexer I.. (context) - Lao, Langmann - 1996
1 Low-Noise, High-Speed Data Transmission Using a RingingCance.. (context) - Sekiguchi - 1995
1 2.8-Gb/s 176-mW Byte-Interleaved and 3.0-Gb/s 118-mW BitInte.. (context) - Kurisu
1 Integrated Circuits for Data Trasmission Over Twisted-Pair C.. (context) - Johns, Essig - 1997
1 Synchronization in Digital System Design (context) - Messerschmit - 1990
1 A 4-GSamp/s Line-Receiver in 0.8m CMOS (context) - Johansson, Yuan et al. - 1996
1 A 100Mb/s Multi-LAN Crosspoint Chip-Set for Cable Management (context) - Le Fevre, Flett - 1997
1 A 200M sample/s 6b flash ADC in 0.6m CMOS (context) - Spalding - 1996
1 A 2-Gb/s Asymmetric Link for High-Bandwidth Packet Switches (context) - Chang - 1997
1 Microwave Connectors and Cable Assemblies (context) - Inc
1 Presentation, Short Course (context) - Gray
1 Probability and Random Processes for Electrial Engineering (context) - Leon-Garcia - 1994
1 CMOS Parallel-Sampling Receivers (context) - Johansson - 1998
1 Low Power Analog Control Clock Synchronizer for 3Gb/s Data R.. (context) - Izzard, Thisell - 1994
Documents on the same site (http://velox.stanford.edu/group/people.html): More
Data Converters for High Speed CMOS Links - Ellersick (2001) (Correct)
Netlist Processing For Custom Vlsi Via Pattern Matching - Chanak (1995) (Correct)
Skew-Tolerant Circuit Design - Harris (1999) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC