Instruction Wake-Up in Wide Issue Superscalars (2001) [7 citations — 0 self]
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Abstract:
Abstract. While the central window implementation in a superscalar processor is an eective approach to waking up ready instructions, this implementation does not scale to large instruction window sizes. We propose a new wake-up algorithm that dynamically associates explicit wake-up lists with executing instructions according to the dependences between instructions. Instead of repeatedly examining a waiting instruction for wake-up till it can be issued, this algorithm identies and considers for wake-up a fresh subset of waiting instructions from the instruction window in each cycle. The direct wake-up microarchitecture (DWMA) that we present is able to achieve approximately 80%, 75 % and 63 % of the performance of a central window processor at high issue widths of 8, 16 and 32 respectively. 1
Citations
| 19 | Superscalar Execution with Dynamic Data Forwarding – Önder, Gipta - 1998 |
| 17 | Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing – Onder, Gupta - 1999 |
| 1 | Scalable Superscalar Processing – Onder, Gupta - 1999 |
