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  MULTI-NODE IMPLICATIONS FOR SEQUENTIAL CIRCUIT REACHABILITY ANALYSIS AND REDUNDANCY IDENTIFICATION

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by Kabir Gulrajani, Kabir Gulrajani
http://www.visc.vt.edu/~mhsiao/papers/thesis_kg99.ps.gz
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Citations

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28 A deductive method of simulating faults in logic circuits – Armstrong - 1972
18 Redundancy Removal for Sequential Circuits Without Reset States – Cheng - 1993
18 FIRE: A FaultIndependent Combinational Redundancy Identi cation Algorithm – Iyer, Abramovici - 1996
10 Low-Cost Redundancy Identification for Combinational Circuits – Iyer, Abramovici - 1994
9 Redundancy identification /removal and test generation for sequential circuits using implicit state enumeration – Cho, Hachtel, et al. - 1993
9 Identifying sequentially untestable faults using illegal states – Long, Iyer, et al. - 1995
8 On Identifying Undetectable and Redundant Faults in Synchronous Sequential Circuits – Pomeranz, Reddy - 1994
7 A transitive closure based algorithm for test generation – Chakradhar, Agrawal - 1991
7 Static Logic Implication with Application to Fast Redundancy Identification – Zhao, Rudnick, et al. - 1997
7 Sequentially Untestable Faults Identified Without Search – Iyer, Abramovici - 1994
5 A method to calculate necessary assignments in ATPG – Rajski, Cox - 1990
5 Dynamic Redundancy Identification in Automatic Test Generation – Abramovici, Miller, et al. - 1992
3 Redundancy Identification Using Transitive Closure – Agrawal, Bushnell, et al. - 1996
1 Accelerated Dynamic Learning for TPG in Combinational Circuits – Kunz, Pradhan - 1993
1 Chakradhar "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits – Agrawal, T - 1995
1 Fast Logic Implication Discovery – Newquist - 1997
1 SOCRATES: A Highly Efficient Test Pattern Generator – Schulz, Trischler, et al. - 1988
1 Multi-Node Implications for Fast Redundancy Identification – Gulrajani, Hsiao - 1999