by Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
http://www.eecg.toronto.edu/~najm/papers/tvlsi02-sumant.ps
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Abstract:
Abstract--- We present a technique, termed clockgenerating (CG) domino, for improving dual-output domino logic that reduces area, clock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24 % respectively over dual-output domino and a 48 % power reduction for the largest circuit.
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Najm received the B.E. degree in electrical engineering from the American University
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worked as Electronics Engineer with AUB from 1983 to 1984
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