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Power Estimation from Hierarchical Netlists  (Make Corrections)  
C.P. Ravikumar Mukul R. Prasad Department of EE-Systems Department of EECS...



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Abstract: We describe a power estimation tool that works at the register-transfer level of abstraction. Such a tool is useful when a transformational based approach is employed to minimize the energy and/or power dissipation in a digital system. Accurate power estimation techniques available in the literature for logic circuits described at gate level prove to be too expensive for data paths in terms of memory as well as execution time. Flattening a hierarchical netlist to gate level is by itself an... (Update)

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BibTeX entry:   (Update)

@misc{ prasad-power,
  author = "Ravikumar Mukul Prasad",
  title = "Power Estimation from Hierarchical Netlists",
  url = "citeseer.ist.psu.edu/499296.html" }
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98   Transition density: A new measure of activity in digital cir.. - Najm - 1993
65   Towards a HighLevel Power Estimation Capability - Najm - 1995
62   Probabilistic treatment of general combinational networks (context) - Parker, McCluskey - 1975
52   HYPER-LP:A system for power minimization using architectural.. (context) - Chandrakasan, Potkonjak et al. - 1992
40   Estimating power dissipation of VLSI signal processing chips.. (context) - Powell - 1990
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38   Power estimation for high level synthesis (context) - Landman, Rabaey - 1993
36   Behavioral Level Power Estimation and Exploration - Mehra, Rabaey - 1994
34   Circuit-activity based logic synthesis for low power reliabl.. (context) - Roy, Prasad - 1993
34   Information theoretic measures of energy consumption at regi.. (context) - Marculescu, Marculescu et al. - 1995
29   Switching activity analysis considering spatiotemporal corre.. - Marculescu, Marculescu et al. - 1994
12   A cell-based power estimation in CMOS combinational circuits (context) - Lin, Liu et al. - 1994
5   Togaps : A testability oriented genetic algorithm for pipeli.. (context) - Ravikumar, Saxena - 1995

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