A 2 GHz CMOS Double Conversion Downconverter with Robust Image Rejection Performance against the Process and Temperature Variations
Abstract:
This paper presents a 2 GHz image rejection (IR) downconverter implemented in a 0.65 µm CMOS technology. It maintains high IR ratio against the process and temperature variations if the on-chip passive RC components are relatively matched. The experimental circuit provides an IR ratio of 40.8 dB without any off-chip filtering or tuning, and dissipates 91 mW at 3.3 V.
Citations
| 97 | The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed – Lee - 1998 |
| 64 | CMOS Analog Circuit Design – Allen, Holberg - 1987 |
| 20 | A Single-Chip 900MHz CMOS Receiver Front-End with a High Performance Low-IF Topology – Crols |
| 12 | et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications – Rudell - 1997 |
| 4 | Single sideband modulation using sequence asymmetric polyphase networks – Gingell - 1973 |
| 1 | Abidi, “CMOS 10 MHz-IF downconverter with on-chip broadband circuit for large image-suppression – Behbahani, Kishigami, et al. - 1999 |
