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Abstract: We present a mathematical definition of a hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore,... (Update)
Context of citations to this paper: More
...Projects Agency, the Office of Naval Research, or the U.S. Government. earlier systems [3, 4, 5, 8, 10, 11, 13, 14, 15, 18, 19, 20, 29, 31, 32, 35, 36, 37, 38, 41, 42, 43] supports the claim that such a logic is sufficiently expressive to permit one to address deep...
...and the communications delay. The correcntess of a gate level design of a device implementing the biphase mark protocol has been proved [32]. The correctness of a gate level design of a device implementing an 8 bit parallel io Byzantine agreement processor has been proved [26]...
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A Formalization of a Subset of VHDL - Russinoff (1994) (Correct)
Design Goals for ACL2 - Kaufmann, Moore (1994) (Correct)
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BibTeX entry: (Update)
D. M. Russinoff. Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. Technical Report 99, Computational Logic, Inc., Austin, Texas, May, 1994. URL http://www.cli.com/. http://citeseer.ist.psu.edu/article/russinoff94specification.html More
@incollection{ russino95specification,
author = "D. Russinoff",
title = "Specification and verification of gate-level VHDL models of synchronous
and asynchronous circuits",
booktitle = "Specification and Validation
Methods",
editor = "E. Borger",
publisher = "Oxford University Press",
pages = "411--459",
year = "1995",
url = "citeseer.ist.psu.edu/article/russinoff94specification.html" }
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