Predicating Which Provides speculative execution reduces the number of cycles for program execution, the...  Home/Search
Context
Related
| shimada.nuee.nagoyau.ac...ISCA96.ps.gz Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: shimada.nuee.nagoyau.a...indexe (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate performance improvement using the number of cycles that are required to execute a program, but do not quantitatively estimate the penalty imposed on the cycle time from the architecture. Since the performance of a microprocessor must be measured by its execution time, a cycle time evaluation is required as well as a... (Update)
Similar documents (at the sentence level):
5.8%: Unconstrained Speculative Execution with Predicated State Buffering - al. (1995) (Correct)
Active bibliography (related documents): More All
0.2: The Multiscalar Architecture - Franklin (1993) (Correct)
0.2: Boosting Beyond Static Scheduling in a Superscalar Processor - Smith, Lam, Horowitz (1990) (Correct)
0.1: Enhancing Multiple-Path Speculative Execution with Predicate.. - Tsai, Yew (Correct)
System load high. Please wait...
Timeout. Please try your query later.
Similar documents based on text: More All
0.5: Efficient Superscalar Performance Through Boosting - Michael Smith Mark (1992) (Correct)
0.4: Instruction Can Be Moved Only If the Operation Maintains Program .. - Legal And (Correct)
0.3: A Global Scheduling Technique for Fine-Grained.. - Malloy, Gupta, Soffa (1995) (Correct)
BibTeX entry: (Update)
@misc{ provides-we,
author = "Predicating Which Provides",
title = "[11]). We recently proposed a mechanism called",
url = "citeseer.ist.psu.edu/486192.html" }
Citations (may not include all citations):1399 Compilers: Principles (context) - Aho, Sethi et al. - 1986
222 MIPS RISC Architecture (context) - Kane - 1988
193 Superscalar Microprocessor Design (context) - Johnson - 1991
185 Branch Prediction Strategies and Branch Target Buffer Design (context) - Lee, Smith - 1984
158 Effective Compiler Support for Predicated Execution Using th.. - Mahlke, Lin et al. - 1992
112 Highly Concurrent Scalar Processing (context) - Hsu, Davidson - 1986
84 Reducing the Cost of Branches (context) - McFarling, Hennessy - 1986
66 Boosting Beyond Static Scheduling in a Superscalar Processor - Smith, Lam et al. - 1990
57 Implementation of Precise Interrupts in Pipelined Processors - Smith, Pleszkun - 1985
8 Unconstrained Speculative Execution with Predicated State Bu.. - Ando, Nakanishi et al. - 1995
6 SIMP (Single Instruction Stream/Multiple Instruction Pipelin.. (context) - Murakami, Irie et al. - 1989
Documents on the same site (http://www.shimada.nuee.nagoya-u.ac.jp/~ando/index-e.html): More
Instruction Can Be Moved Only If the Operation Maintains Program .. - Legal And (Correct)
Unconstrained Speculative Execution with Predicated State Buffering - al. (1995) (Correct)
An On-Chip Multiprocessor Architecture with a Non-Blocking.. - Kobayashi, al. (1999) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC