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Abstract: In vector multiprocessor systems, collisions in the interconnection network and conflicts in the memory modules are the main causes of the performance degradation. In this work we propose to synchronize the access to the memory system so that streams can be accessed with the minimum achievable latency if their elements are requested out of order. The mechanism uses a blockinterleaved storage scheme and works for strides belonging to the most common families of strides found in real... (Update)
Context of citations to this paper: More
.... into establishing a global arbitration of the accesses, so that the memory module that each port can request at each cycle is pre defined [20]; for simplicity, we make that each port visits the memory modules in lexicographical order. The global arbitration is expressed by a...
Cited by: More
Vector Multiprocessors With Arbitrated Memory Access - Montse Peiron Mateo (1995) (Correct)
Vector Multiprocessors with Arbitrated Memory Access - Peiron, Valero.. (1995) (Correct)
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1.7: Memory Access Synchronization in Vector Multiprocessors - Mateo Valero Montse (1994) (Correct)
0.3: Synchronized Access To Streams In Multiprocessors - Montse Peiron Mateo (1993) (Correct)
0.1: Conflict-Free Access to Streams in - Multiprocessor Systems Peiron (1993) (Correct)
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1.3: Network Synchronization And Out-Of-Order Access To Vectors - Mateo Valero Eduard (Correct)
1.2: Conflict-Free Access to Streams in Multiprocessor Systems - Peiron, Valero.. (1993) (Correct)
1.1: Conflict-Free Access For Streams In Multi-Module Memories - Mateo Valero Toms (1993) (Correct)
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2: The Organization and Use of Parallel Memories (context) - Budnik, Kuck - 1971
2: Vector computer memory bank contention - Bailey - 1987
2: Increasing the Number of Strides for Conflict-Free Vector Access (context) - Valero - 1992
BibTeX entry: (Update)
M. Valero, M. Peiron and E. Ayguad, "Memory Access Synchronization in Vector Multiprocessors", CONPAR http://citeseer.ist.psu.edu/480873.html More
@inproceedings{ valero94memory,
author = "Mateo Valero and Montse Peiron and Eduard Ayguade",
title = "Memory Access Synchronization in Vector Multiprocessors",
booktitle = "Conference on Algorithms and Hardware for Parallel Processing",
pages = "414-425",
year = "1994",
url = "citeseer.ist.psu.edu/480873.html" }
Citations (may not include all citations):97 The Architecture of Pipelined Computers (context) - Kogge - 1981
78 Data Prefetching in Multiprocessor Vector Cache Memories (context) - Fu, Patel - 1991 ACM DBLP
44 The IBM Research Parallel Processor Prototype (RP3): Introdu.. (context) - Pfister - 1985 DBLP
40 Increasing the Number of Strides for Conflict-Free Vector Ac.. (context) - Valero, Lang - 1992 ACM DBLP
38 The Organization and Use of Parallel Memories (context) - Budnik, Kuck - 1971
21 XOR-schemes: A Flexible Data Organization in Parallel Memori.. (context) - Frailong, Jalby et al. - 1985 DBLP
15 The Cydra 5 Stride-Insensitive Memory System (context) - Rau, Schlansker et al. - 1989
14 Interleaved Parallel Schemes: Improving Memory Throughput on.. (context) - Seznec, Lenfant - 1992 DBLP
9 A Conflict-free Memory Design for Multiprocessors - Shing, Ni - 1991 ACM DBLP
8 Introducing a New Cache Design into Vector Computers (context) - Yang - 1993 ACM DBLP
5 Synchronized Access to Streams in SIMD Vector Multiprocessor.. (context) - Peiron, Valero et al. - 1994 ACM DBLP
2 Optimal Access to Streams in Multimodule Memories (context) - Valero, Peiron et al.
2 Synchronized Access to Streams in Multiprocessors - Peiron, Valero - 1993
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