Abstract:
Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are avalaible, it still represents one of the major bottlenecks of many digital systems that require intensive and fast computations. This paper presents a novel design approach based on the well-known Baugh and Wooley algorithm, particularly appealing for asynchronous implementations and that may be easily mapped into a VLSI circuit. This technique has been applied to the design of a high-speed variable-delay multiplier that resulted to be faster than other synchronous and asynchronous implementations. 1
Citations
|
62
|
Some schemes for parallel multipliers
– Dadda
- 1965
|
|
55
|
Asynchronous Circuits
– Brzozowski, Seger
- 1995
|
|
51
|
A signed binary multiplication technique
– Booth
- 1951
|
|
37
|
A Two’s Complement Parallel Array Multiplication Algorithm
– Baugh, Wooley
- 1973
|
|
33
|
On-the-fly conversion of redundant into conventional representations
– Ercegovac, Lang
- 1987
|
|
26
|
Speculative completion for the design of high-performance asynchronous dynamic adders
– Nowick, Yun, et al.
- 1997
|
|
23
|
Conditional Sum Addition Logic
– Sklansky
- 1960
|
|
23
|
Heuristic minimization of multiple-valued relations
– Watanabe, Brayton
- 1993
|
|
14
|
Boolean Relations and the Incomplete Specification of Logic Networks
– Brayton, Somenzi
- 1989
|
|
9
|
High-Radix Division and Square Root with Speculation
– Cortadella, Lang
- 1994
|
|
6
|
Carry-Save Multiplication Schemes Without Final Addition
– Ciminiera, Montuschi
- 1996
|
|
6
|
Statistical Carry Lookahead Adders
– Gloria, Olivieri
- 1996
|
|
5
|
Bundled Data Asynchronous Multipliers with Data Dependent Computation Times
– Kearney, Bergmann
- 1997
|
|
5
|
A low power zero-overhead self-timed division and square root unit combining a singlerail static circuit with a dual-rail dynamic circuit
– Matsubara, Ide
- 1997
|
|
4
|
A 160ns 54-bit CMOS Division Implementation Using Self-Timing and Simmetrically Overlapped SRT Stages
– Williams, Horowitz
- 1991
|
|
3
|
Elmasry, \Low-Power Digital VLSI Design
– Bellaouar, I
- 1995
|
|
1
|
et al. Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
– Benini, Micheli, et al.
- 1999
|
|
1
|
Design and Analysis of Variable-Delay Arithmetic Units
– Cornetta
- 2001
|
