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Abstract:

We present SCORE (Stream Computations Organized for Reconfigurable Execution), a multi-threaded model that relies on streams to expose thread parallelism and to enable efficient scheduling, low-overhead communication, and scalability. We present work to-date on SCORE for scalable reconfigurable logic, as well as implementation ideas for SCORE for processor architectures. We demonstrate that streams can be exposed as a clean architectural feature that supports forward compatibility to larger, more parallel hardware. 1. OVERVIEW For the past several decades, the predominant architectural abstraction for programmable computation systems has been the instruction set architecture (ISA). An ISA defines an instruction set and semantics for executing it. A key benefit of the ISA model is that those semantics decouple software from hardware development. A piece of software, written and compiled once, is guaranteed to run on any ISA-compatible device. This guarantee allows hardware to evolve over time, growing larger and faster with each process generation. The existing software base is preserved, and its performance automatically improves with each hardware generation. The ISA abstraction has been instrumental in protecting our investment in software and allowing it to ride Moore’s law to better performance. Two shining examples are the IBM 360 and Intel x86 architectures, which have survived commercially for decades. The latter, in its 23 years of existence, has seen clock speeds increase nearly 400x and transistor counts grow nearly 10,000x. 1 Increasingly, however, ISA uniprocessors are running out of headroom for performance improvement, due primarily to the increasing costs of extracting and exploiting instruction level parallelism (ILP). Today’s state-of-the

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