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Abstract:

The state-of-the-art microprocessor employs tens of millions of transistors on a single chip, most of them are used to tackle the problem of slow memory. While these processors demonstrate great benchmark ratings, they do not necessarily work well on a lot of real world applications. On the other hand, memory components oer huge numbers of transistors that could be utilized to do signicant work thanks to major advances in Merged Logic DRAM technology. In this thesis a novel architecture is proposed to bridge the memory/processor speed gap in a much more cost eective way than the traditional central processor. Also parallelism is exploited using simple processor arrays thus surmounting the limit of ILP. The combined eect has very promising results. Assuming conservative parameters for the proposed system while using aggressive parameters for a traditional reference system, we get an average speedup of 7.8 and best case of 36 for ve benchmarks only with a single memory chip. iii To My Parents, for their endless love and support. iv ACKNOWLEDGMENTS First and foremost I would like to thank my advisor Josep Torrellas for his guidance and support over the past few years, which made the completion of this thesis possible. Secondly, my gratitude goes to all the IACOMA group members, current and past,

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