Ney L. V. Calazans, Fernando G. Moraes, Katherine B. Quintans, Felipe B....  Home/Search
Context
Related
| inf.pucrs.br/~mora...000_core_quick.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: inf.pucrs.br/~moraes/FMpapers (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This paper is dedicated to explore the acceleration of sorting algorithms with reconfigurable hardware. We present the rationale for solving the sorting problem in hardware, and suggest ways to ease the use of sorting hardware in the real world of applications programming. One of the ongoing work main goals is the migration of the quicksort algorithm to hardware. The algorithm and its mapping to hardware are discussed. Keywords: sorting, VHDL, FPGA, digital systems, fast prototyping. 1 (Update)
Active bibliography (related documents): More All
0.0: Scalable Sweeping-Based Spatial Join - Arge, Procopiuc, Ramaswamy, Suel.. (1998) (Correct)
0.0: Communication Conscious Radix Sort - Jiménez-González.. (1999) (Correct)
0.0: Nsort: a Parallel Sorting Program for NUMA and SMP.. - Nyberg, Koester, Gray (1997) (Correct)
Similar documents based on text: More All
0.6: Transitional Behaviors of the Average Cost of Quicksort With.. - Chern, Hwang (2001) (Correct)
0.5: Teaching Computer Organization and Architecture with.. - Calazans, Moraes, Marcon (2002) (Correct)
0.5: Deriving Different Computer Science Curricula from a.. - Moraes, Zorzo, Calazans (2002) (Correct)
BibTeX entry: (Update)
@misc{ fernando-accelerating,
author = "Ney Calazans Fernando",
title = "Accelerating Sorting With Reconfigurable Hardware",
url = "citeseer.ist.psu.edu/460867.html" }
Citations (may not include all citations):3972 Introduction to algorithms (context) - Cormen - 1990
113 The Design and Analysis of Parallel Algorithms (context) - Akl - 1989
61 AlphaSort: A RISC Machine Sort (context) - ii
55 High-Performance Sorting on Networks of Workstations (context) - ii - 1997
1 A Super Scalar Sorting Algorithm for RISC Processors (context) - Agarwal
Documents on the same site (http://www.inf.pucrs.br/~moraes/FMpapers.html): More
Interconnection Length Estimation at Logic-Level - Martins, Moraes, Reis (2001) (Correct)
A New Layout Style For High-Performance Circuits - Moraes (Correct)
Hardware/Software Implementation for Localization.. - Molz, Engel.. (2001) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC