Abstract:
The automatic layout synthesis for random logic circuits is the solution to obtain the best trade-off between area, delay and power. Classic approaches, like standard-cells, have area and power consumption penalized, since the basic cells are over-sized to supply strong output loads eventually needed. This paper presents a new layout style to generate random logic circuits, developing 3 characteristics to improve electrical performances: reduction of parasitic capacitances (minimum use of polisilicon layer and cell synthesis with minimum number of diffusion gaps), transistor sizing without changes in placement and routing (resulting in constant area for different sizing solutions) and use of 3 metal layers and stacked contacts for routing. I.
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