Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay S. Lee  Home/Search
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Abstract: Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, parallelism has been exploited either at the instruction level with a grain-size of a single instruction or by partitioning applications into coarse threads with grain-sizes of thousands of instructions. Fine--grain threads fill the parallelism gap between these extremesby enabling tasks with run lengths as small as 20... (Update)
Context of citations to this paper: More
.... HEP [Smith81] Tera [Alverson90] and Alewife [Kranz92] They are also similar to the pre and post condition mechanism of the M Machine [Keckler98], which differs from the others in that instead of causing a trap, a failure sets a predicate register which must be explicitly...
...d2) In the patterns, the arrows represent detected data races. of the new epoch very quickly and without software intervention (e.g. [5, 10, 13]) One difference in ReEnact is in the way epochs are terminated and started. An epoch terminates by default when it reaches a...
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BibTeX entry: (Update)
S.W. Keckler, W.J. Dally, D. Maskit, N.P. Carter, A. Chang, and W.S. Lee. Exploiting fine-grain thread level parallelism on the MIT multi-alu processor. In 25th Annual International Symposium on Computer Architecture, June 1998. http://citeseer.ist.psu.edu/article/keckler98exploiting.html More
@inproceedings{ keckler98exploiting,
author = "Stephen W. Keckler and William J. Dally and Daniel Maskit and Nicholas P. Carter and Andrew Chang and Whay Sing Lee",
title = "Exploiting Fine-grain Thread Level Parallelism on the {MIT} Multi-{ALU} Processor",
booktitle = "{ISCA}",
pages = "306-317",
year = "1998",
url = "citeseer.ist.psu.edu/article/keckler98exploiting.html" }
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251 Simultaneous multithreading: Maximizing on-chip parallelism - TULLSEN, EGGERS et al. - 1995
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156 The multiflow trace scheduling compiler - LOWNEY, FREUDENBERGER et al. - 1993
127 A multithreaded massively parallel architecture (context) - NIKHIL, PAPADOPOULOS et al. - 1992
104 for semiconductors. Semiconductor Industry Association (context) - technology - 1997
56 Machine Multicomputer (context) - FILLO, KECKLER et al. - 1995
38 Evaluation of design alternatives for a multiprocessor micro.. (context) - NAYFEH, HAMMOND et al. - 1996
35 The impact of synchronization and granularity on parallel sy.. - CHEN, SU et al. - 1990
25 Department of Electrical Engineering and Computer Science (context) - GUREVICH - 1995
16 Experience with fine-grain synchronization in MIMD machines .. - YEUNG, AGARWAL - 1993
6 Thread prioritization: A thread scheduling mechanism for mul.. - FISKE, DALLY - 1995
3 A highperformance Lisp (context) - KRANZ, HALSTEAD et al. - 1989
2 Springer-Verlag (context) - ROBBINS, ROBBINS - 1987
1 Application performanceon the MIT alewife machine (context) - CHONG, LIM et al. - 1996
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