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Abstract: This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8 x 8 elements of 8 bits each is processed in 25.2s and the pipeline latency is 160 clock cycles. 1. (Update)
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BibTeX entry: (Update)
@misc{ agostini-dct,
author = "Luciano Agostini and Ivan Saraiva Silva and Sergio Bampi",
title = "2-D DCT Architecture for Image Compression",
url = "citeseer.ist.psu.edu/451960.html" }
Citations (may not include all citations):358 JPEG Still Image Data Compression Standard (context) - PENNEBAKER, MITCHELL - 1992
86 Image and Video Compression Standards Algorithms and Archite.. (context) - BHASKARAN, KONSTANTINIDES - 1999
39 The International Telegraph and Telephone Consultative Commi.. (context) - Telegraph, Committee et al. - 1992
36 A Fast DCT-SQ Scheme for Images (context) - ARAI, AGUI et al. - 1988
24 Fast Algorithms for the Discrete Cosine Transform (context) - FEIG, WINOGRAD - 1992
4 A Cost-Effective Architecture for 8 x 8 Two-Dimensional DCT/.. (context) - LEE, CHEN et al. - 1997
4 A 100 MHz 2-D 8 x 8 DCT/IDCT Processor for HDTV Applications (context) - MADISETTI, WILLSON - 1995
3 JAGUAR: A Fully Pipeline VLSI Architecture for JPEG Image Co.. (context) - KOVAC, RANGANATHAN - 1995
2 High-Throughput VLSI Architectures for the 1-D and 2D Discre.. (context) - WANG, CHEN - 1995
1 Projeto de uma Arquitetura de DCT 1D para a Compresso de Ima.. (context) - AGOSTINI, BAMPI - 2001
1 Altera Digital Library (context) - Corporation - 2000
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