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Abstract: This paper presents a new scheme for scheduling and control synthesis in high-level circuit design. The scheduling algorithm tries to maximize the performance of a design under resource constraints by maximizing the utilization of resources and minimizing clock slack. It exploits the technique of bit-level chaining (BLC) to target high-speed design. It also exploits noninteger multicycling and chaining, which allows multiple cycle execution of a set of chained operations and even sharing of... (Update)
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BibTeX entry: (Update)
S. Park and K. Choi, "Performance-driven High-Level Synthesis with Bit-Level Chaining and Clock Selection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 199-212, Feb 2001. http://citeseer.ist.psu.edu/article/park01performancedriven.html More
@misc{ park01performancedriven,
author = "S. Park and K. Choi",
title = "Performance-driven High-Level Synthesis with Bit-Level Chaining and Clock
Selection",
text = "S. Park and K. Choi, Performance-driven High-Level Synthesis with Bit-Level
Chaining and Clock Selection, IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol. 20, no. 2, pp. 199-212, Feb 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/article/park01performancedriven.html" }
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