Adaptive Explicitly Parallel Instruction Computing

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Adaptive Explicitly Parallel Instruction Computing (2000) (Make Corrections) (6 citations)
Surendranath Talla

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Abstract: Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set while generating code for a given application. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. 1. Can application performance be improved if... (Update)

Context of citations to this paper: More

...to study the benefits of various functional units and interconnect structures. Adaptive Explicitly Parallel Instruction Computing [26] and Dynamically Variable Instruction Set Architecture [20] represent notable works in this research area. Our approach starts from a...

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ACRES Architecture and Compilation - Ang, Schlansker (2004) (Correct)
A Co-simulation Study of Adaptive EPIC Computing - Valentin Stefan Gheorghita (Correct)

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BibTeX entry: (Update)

S. Talla. Adaptive Explicitly Parallel Instruction Computing. PhD thesis, New York University, 2000. http://citeseer.ist.psu.edu/article/talla00adaptive.html More

@phdthesis{ talla00adaptive,
    author = "Surendranath Talla",
    title = "Adaptive explicitly parallel instruction computing",
    year = "2000",
    url = "citeseer.ist.psu.edu/article/talla00adaptive.html" }

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