Karthikeyan Sankaralingam, Ramadass Nagarajan, Stephen W. Keckler, Doug Burger  Home/Search
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Abstract: CMOS technology scaling poses challenges in designing dynamically scheduled cores that can sustain both high instruction-level parallelism and aggressive clock frequencies. In this paper, we present a new architecture that maps compiler-scheduled blocks onto a two-dimensional grid of ALUs. For the mapped window of execution, instructions execute in a dataflow-like manner, with each ALU forwarding its result along short wires to the consumers of the result. We describe our studies of program... (Update)
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BibTeX entry: (Update)
K. Sankaralingam, R. Nagarajan, D.C. Burger, and S.W. Keckler. A TechnologyScalable Architecture for Fast Clocks and High ILP. In 5th Workshop on the Interaction of Compilers and Computer Architecture, January 2001. http://citeseer.ist.psu.edu/article/sankaralingam01technologyscalable.html More
@misc{ sankaralingam01technologyscalable,
author = "K. Sankaralingam and R. Nagarajan and D. Burger and S. Keckler",
title = "A TechnologyScalable Architecture for Fast Clocks and High ILP",
text = "K. Sankaralingam, R. Nagarajan, D.C. Burger, and S.W. Keckler. A TechnologyScalable
Architecture for Fast Clocks and High ILP. In 5th Workshop on the Interaction
of Compilers and Computer Architecture, January 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/article/sankaralingam01technologyscalable.html" }
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