1 USING MULTIPLE BLOCK BUFFERS AND BIT LINE ISOLATION FOR LOW POWER SUPERSCALAR PROCESSOR CACHES
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Abstract:
On--chip caches in high end superscalar microprocessors dissipate a large fraction of the total power due to high density of transistors and high operating frequency. Organizational techniques such as block buffering and subbanking have been observed to provide substantial energy savings in a technology independent manner. We propose and evaluate the advantages of using multiple block buffers and bit line isolation without compromising the cache cycle time in on--chip caches for superscalar CPUs. We also study the behavior of on--chip cache power with the degree of instruction dispatch in the superscalar pipeline. A superscalar cache power estimation tool (SCAPE) is used to simulate the execution of SPEC95 benchmarks and measure the transition activity within the various cache components. The transition counts are fed into an energy dissipation model for a 0.8 micron cache to estimate the power dissipation within various cache components. We show that the use of 4--8 block buffers provide an additional saving of 31--38 % over single block buffer and when used in conjunction with subbanking and bit line isolation, a substantial reduction of 70--75 % is achievable compared to conventional caches 1.
