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Abstract: A new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMOS circuits has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL... (Update)
Context of citations to this paper: More
...are enabled using a predischarged NMOS tree with the performance advantages of a precharged CVSL design. Previous versions of DCSL [10], while achieving these goals were limited to high supply to threshold voltage ratios (V DD 3V t ) because of a large number of stacked...
...Fig. 1 shows the schematic of the proposed CSDL. It employs the same number of transistors as differential current switch logic (DCSL) in [5], consisting of a complementary nMOS logic tree, pull up transistors, two inverters, and five clocked transistors for precharge and...
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2: Cascode voltage switch logic: A differential CMOS logic family (context) - Heller, Griffin et al. - 1984
2: Sample-set differential logic (SSDL) for complex high speed VLSI (context) - Grotjohn, Hoefflinger - 1986
BibTeX entry: (Update)
Dinesh Somasekhar, Kaushik Roy, "Differential Current Switch Logic: A Low Power DCVS Logic Family", IEEE J. Solid State Circuits, June http://citeseer.ist.psu.edu/43483.html More
@misc{ somasekhar-differential,
author = "D. Somasekhar and K. Roy",
title = "Differential Current Switch Logic: A Low Power DCVS Logic Family",
text = "Dinesh Somasekhar, Kaushik Roy, Differential Current Switch Logic: A Low
Power DCVS Logic Family, IEEE J. Solid State Circuits, June",
url = "citeseer.ist.psu.edu/43483.html" }
Citations (may not include all citations):17 Cascode voltage switch logic: A differential CMOS logic fami.. (context) - Heller, Griffin et al. - 1984
14 Comparison of CMOS Circuit Techniques: Differential Cascode .. (context) - Chu, Pulfrey - 1987
5 Latched CMOS Differential Logic (LCDL) for Complex High-Spee.. (context) - Chung-Yu, Kuo-Hsing - 1991
4 A Comparative Study on CMOS digital Circuit Families for Low.. (context) - Lee, Ko et al. - 1994
4 Evaluation of twosummand adders implemented in ECDL CMOS dif.. (context) - Shih-Lien, Milos et al. - 1991
4 Design of self-checking circuits using DCVS logic: A case st.. (context) - Kanopoulos - 1992
3 Sample-set differential logic (SSDL) for complex high speed .. (context) - Grotjohn, Hoefflinger - 1986
3 Design and implementation of a totally self-checking 16 mult.. (context) - Kanopoulos, Carabetta - 1992
2 Implementation of Iterative Networks with CMOS Differential .. (context) - Lu - 1988
2 A 4.4ns CMOS 54 \Theta 54-b Multiplier Using Pass-Transistor.. (context) - Ohkubo - 1995
2 SODS: A New CMOS Differential-Type Structure (context) - Acosta, Valencia et al. - 1995
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