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Analysis of Different Protocol Descriptions Styles in VHDL to High-Level Synthesis (1996)  (Make Corrections)  (4 citations)
L. Pirmez, A. Pedroza, A. Mesquita, M. Rahmouni, P. Kission, A. Jerraya



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Abstract: A methodology based on VHDL to obtain protocol descriptions suitable to be synthesized using AMICAL, a VHDL based behavioral synthesis tool, is presented. In order to efficiently obtain synthesized architectures, a number of constraints must be imposed on the writing style of VHDL. An example based on the specification of a high speed protocol is discussed. (Update)

Context of citations to this paper:   More

.... for digital systems design automation [3] The starting point of the design process is a VHDL system level behavioral description [4] of the protocol similar to the protocol functional specification that is mapped into a structural description through HLS techniques....

.... will depend on the type and order of statements used in the HLS input description, which characterizes a description style [9]. To illustrate this fact, consider the ISO s ABRACADABRA reference protocol modelled by state machines that interact through the exchange of...

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4:   Cadence Online Library (context) - Systems - 1994
4:   IEEE Standard VHDL Language Reference Manual (context) - Inc - 1988
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BibTeX entry:   (Update)

L. Pirmez, M. Rahmouni, P. Kission, A. Pedroza, A. C. Mesquita and A. A. Jerraya, "Analysis of different protocol description styles in VHDL to high-level synthesis", in EURODAC '96, Geneve, 1996. http://citeseer.ist.psu.edu/article/pirmez96analysis.html   More

@misc{ pirmez96analysis,
  author = "L. Pirmez and M. Rahmouni and P. Kission and A. Pedroza and A. Mesquita
    and A. Jerraya",
  title = "Analysis of different protocol description styles in VHDL to high-level
    synthesis",
  text = "L. Pirmez, M. Rahmouni, P. Kission, A. Pedroza, A. C. Mesquita and A. A.
    Jerraya, Analysis of different protocol description styles in VHDL to high-level
    synthesis, in EURODAC '96, Geneve, 1996.",
  year = "1996",
  url = "citeseer.ist.psu.edu/article/pirmez96analysis.html" }
Citations (may not include all citations):
217   High Level Synthesis : Introduction to Chip and System Desig.. (context) - Gajski - 1992
65   An Introduction to Estelle : A Specification Language for Di.. (context) - Budkowski, Dembinski - 1987
49   Path-Based Scheduling for Synthesis (context) - Camposano - 1991
44   A Survey of High-Level Synthesis Systems (context) - Walter, Camposano - 1991
10   Data Transport in a Byte Stream Network (context) - Fraser, Marshall - 1989
8   Communications Protocols for High Speed Packet Networks (context) - Doshi, Johri - 1992
7   Structured Design Methodology for High-Level Design (context) - Kission, Ding - 1994
7   VHDL Based Design Methodology for Hierarchy and Component Re.. (context) - Kission, Ding et al. - 1995
6   A Powerful Dialect of Estelle for OSI Protocol Description (context) - Courtiat - 1988
5   Formulation and Evaluation of Scheduling Techniques for Cont.. (context) - Rahmouni, Jerraya - 1995
4   A Methodology to the Implementation of Distributed System in.. (context) - Pirmez, Pedroza et al. - 1995
4   A Methodology to the Implementation of Distributed System in.. (context) - Pirmez - 1995
4   Computer Science (context) - Ashenden - 1990
3   AMICAL: Architectural Synthesis Based on VHDL (context) - Park, O'Brien et al. - 1993
3   A Loop-based Scheduling Algorithm For Hardware Description L.. (context) - Rahmouni, 'Brien et al. - 1994
2   A Methodology to Developed Integrated Circuits from Estelle .. (context) - Pirmez, Carneiro et al. - 1995
2   Industrial Experimentation of High-Level Synthesis (context) - Kission, Closse et al. - 1993
1   special issue on High-Level Synthesis (context) - Bhasker, Lee - 1990
1   A High-Level Language for Design and Modeling of Hardware (context) - Navabi - 1992
1   Introduction to High_Level Synthesis (context) - Gajski, Ramachandran - 1994
1   VHDL as Input for High_Level Synthesis (context) - Camposano, Saunders et al. - 1991

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