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  Correctness of Pipelined Machines (2000) [17 citations — 7 self]

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by Panagiotis Manolios
Formal Methods in Computer-Aided Design–FMCAD 2000, volume 1954 of LNCS
http://www.cs.utexas.edu/users/pete/pub/pipeline.ps.gz
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Abstract:

Abstract. The correctness of pipelined machines is a subject that has been studied extensively. Most of the recent work has used variants of the Burch and Dill notion of correctness [4]. As new features are modeled, e.g., interrupts, new notions of correctness are developed. Given the plethora of correctness conditions, the question arises: what is a reasonable notion of correctness? We discuss the issue at length and show, by mechanical proof, that variants of the Burch and Dill notion of correctness are awed. We propose a notion of correctness based on WEBs (Well-founded Equivalence Bisimulations) [16, 19]. Brie y, our notion of correctness implies that the ISA (Instruction Set Architecture) and MA (Micro-Architecture) machines have the same observable innite paths, up to stuttering. This implies that the two machines satisfy the same CTL nX properties and the same safety and liveness properties (up to stuttering). To test the utility of the idea, we use ACL2 to verify several variants of the simple pipelined machine described by Sawada in [22, 23]. Our variants extend the basic machine by adding exceptions (to deal with over ows), interrupts, and eshed-out 128-bit ALUs (one of which is described in a netlist language). In all cases, we prove the same nal theorem. We develop a methodology with mechanical support that we used to verify Sawada's machine. The resulting proof is substantially shorter than the original and does not require any intermediate abstractions; in fact, given the denitions and some general-purpose books (collections of theorems), the proof is automatic. A practical and noteworthy feature of WEBs is their compositionality. This allows us to prove the correctness of the more elaborate machines in manageable stages. 1

Citations

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147 Computer-Aided Reasoning: An Approach – Kaufmann, Manolios, et al. - 2000
75 Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking – McMillan - 1998
54 ACL2 Theorems about Commercial Microprocessors – Brock, Kaufmann, et al. - 1996
51 Deciding equality formulas by small-domain instantiations – Pnueli, Rodeh, et al. - 1999
41 Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions – Bryant, German, et al. - 1999
37 Concurrency and automata on in sequences – Park - 1981
33 Trace Table based Approach for Pipelined Microprocessor Verification. CAV – Sawada, Hunt - 1997
28 Structured theory development for a mech-anized logic – Kaufmann, Moore - 2001
27 G.Gopalakrishnan, “Proof of correctness of a processor with reorder buffer using the completion functions approach – Hosabettu - 1999
22 A correctness model for pipelined microprocessors – Windley, Coe
19 Characterizing Kripke structures in propositional temporal logic – Browne, Clarke, et al. - 1988
19 Automatic Veri of Pipelined Microprocessor Control – Burch, Dill - 1994
16 A Simple Characterization of Stuttering Bisimulation – Namjoshi - 1997
10 Linking theorem proving and modelchecking with well-founded bisimulation – Manolios, Namjoshi, et al. - 1999
8 Verification of a Simple Pipelined Machine Model – Sawada - 2000
7 Processor veri with precise exceptions and speculative execution – Sawada, Hunt - 1998
5 Microprocessor veri in PVS: A methodology and simple example – Cyrluk - 1993
4 Homepage of Panagiotis Manolios – Manolios - 2000
4 Formal Veri of an Advanced Pipelined Machine – Sawada - 1999
4 Formal veri of a pipelined microprocessor – Srivas, Bickford - 1990
3 A proof of correctness of a processor implementing Tomasulo's algorithm without a reorder buer – Hosabettu, Gopalakrishnan, et al. - 1999
2 Assume-guarantee re between dierent time scales – Henzinger, Qadeer, et al. - 1999
2 Well-founded equivalence bisimulation – Manolios - 2000
2 Formal veri of an avionics microprocessor – Srivas, Miller - 1995
1 Decomposing the proof of correctness of a pileplined microprocessors – Hosabettu, Srivas, et al. - 1998